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Demo blink sketch for first test

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This commit is contained in:
Moritz Martinius
2020-11-07 12:48:40 +01:00
parent 376a9bee91
commit 66bea6372f
969 changed files with 615038 additions and 0 deletions
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rusci-firmware/build/main.d Normal file
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build/main.o: Core/Src/main.c Core/Inc/main.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h \
Core/Inc/stm32f1xx_hal_conf.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h \
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h \
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h \
Drivers/CMSIS/Include/core_cm3.h Drivers/CMSIS/Include/cmsis_version.h \
Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h \
Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h
Core/Inc/main.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h:
Core/Inc/stm32f1xx_hal_conf.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h:
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h:
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h:
Drivers/CMSIS/Include/core_cm3.h:
Drivers/CMSIS/Include/cmsis_version.h:
Drivers/CMSIS/Include/cmsis_compiler.h:
Drivers/CMSIS/Include/cmsis_gcc.h:
Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h:
Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h:

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rusci-firmware/build/main.lst Normal file
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ARM GAS /tmp/ccZ9xwps.s page 1
1 .cpu cortex-m3
2 .eabi_attribute 20, 1
3 .eabi_attribute 21, 1
4 .eabi_attribute 23, 3
5 .eabi_attribute 24, 1
6 .eabi_attribute 25, 1
7 .eabi_attribute 26, 1
8 .eabi_attribute 30, 1
9 .eabi_attribute 34, 1
10 .eabi_attribute 18, 4
11 .file "main.c"
12 .text
13 .Ltext0:
14 .cfi_sections .debug_frame
15 .section .text.MX_GPIO_Init,"ax",%progbits
16 .align 1
17 .arch armv7-m
18 .syntax unified
19 .thumb
20 .thumb_func
21 .fpu softvfp
23 MX_GPIO_Init:
24 .LFB68:
25 .file 1 "Core/Src/main.c"
1:Core/Src/main.c **** /* USER CODE BEGIN Header */
2:Core/Src/main.c **** /**
3:Core/Src/main.c **** ******************************************************************************
4:Core/Src/main.c **** * @file : main.c
5:Core/Src/main.c **** * @brief : Main program body
6:Core/Src/main.c **** ******************************************************************************
7:Core/Src/main.c **** * @attention
8:Core/Src/main.c **** *
9:Core/Src/main.c **** * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
10:Core/Src/main.c **** * All rights reserved.</center></h2>
11:Core/Src/main.c **** *
12:Core/Src/main.c **** * This software component is licensed by ST under BSD 3-Clause license,
13:Core/Src/main.c **** * the "License"; You may not use this file except in compliance with the
14:Core/Src/main.c **** * License. You may obtain a copy of the License at:
15:Core/Src/main.c **** * opensource.org/licenses/BSD-3-Clause
16:Core/Src/main.c **** *
17:Core/Src/main.c **** ******************************************************************************
18:Core/Src/main.c **** */
19:Core/Src/main.c **** /* USER CODE END Header */
20:Core/Src/main.c **** /* Includes ------------------------------------------------------------------*/
21:Core/Src/main.c **** #include "main.h"
22:Core/Src/main.c ****
23:Core/Src/main.c **** /* Private includes ----------------------------------------------------------*/
24:Core/Src/main.c **** /* USER CODE BEGIN Includes */
25:Core/Src/main.c ****
26:Core/Src/main.c **** /* USER CODE END Includes */
27:Core/Src/main.c ****
28:Core/Src/main.c **** /* Private typedef -----------------------------------------------------------*/
29:Core/Src/main.c **** /* USER CODE BEGIN PTD */
30:Core/Src/main.c ****
31:Core/Src/main.c **** /* USER CODE END PTD */
32:Core/Src/main.c ****
33:Core/Src/main.c **** /* Private define ------------------------------------------------------------*/
ARM GAS /tmp/ccZ9xwps.s page 2
34:Core/Src/main.c **** /* USER CODE BEGIN PD */
35:Core/Src/main.c **** #define PIN_RELAY_USB GPIO_PIN_0
36:Core/Src/main.c **** #define PIN_RELAY_GP GPIO_PIN_1
37:Core/Src/main.c **** #define PIN_USB_NOT_OE GPIO_PIN_2
38:Core/Src/main.c **** #define PIN_USB_S GPIO_PIN_3
39:Core/Src/main.c **** #define PIN_USER_LED GPIO_PIN_4
40:Core/Src/main.c **** /* USER CODE END PD */
41:Core/Src/main.c ****
42:Core/Src/main.c **** /* Private macro -------------------------------------------------------------*/
43:Core/Src/main.c **** /* USER CODE BEGIN PM */
44:Core/Src/main.c ****
45:Core/Src/main.c **** /* USER CODE END PM */
46:Core/Src/main.c ****
47:Core/Src/main.c **** /* Private variables ---------------------------------------------------------*/
48:Core/Src/main.c **** CAN_HandleTypeDef hcan;
49:Core/Src/main.c ****
50:Core/Src/main.c **** /* USER CODE BEGIN PV */
51:Core/Src/main.c ****
52:Core/Src/main.c **** /* USER CODE END PV */
53:Core/Src/main.c ****
54:Core/Src/main.c **** /* Private function prototypes -----------------------------------------------*/
55:Core/Src/main.c **** void SystemClock_Config(void);
56:Core/Src/main.c **** static void MX_GPIO_Init(void);
57:Core/Src/main.c **** static void MX_CAN_Init(void);
58:Core/Src/main.c **** /* USER CODE BEGIN PFP */
59:Core/Src/main.c ****
60:Core/Src/main.c **** /* USER CODE END PFP */
61:Core/Src/main.c ****
62:Core/Src/main.c **** /* Private user code ---------------------------------------------------------*/
63:Core/Src/main.c **** /* USER CODE BEGIN 0 */
64:Core/Src/main.c ****
65:Core/Src/main.c **** /* USER CODE END 0 */
66:Core/Src/main.c ****
67:Core/Src/main.c **** /**
68:Core/Src/main.c **** * @brief The application entry point.
69:Core/Src/main.c **** * @retval int
70:Core/Src/main.c **** */
71:Core/Src/main.c **** int main(void)
72:Core/Src/main.c **** {
73:Core/Src/main.c **** /* USER CODE BEGIN 1 */
74:Core/Src/main.c ****
75:Core/Src/main.c **** /* USER CODE END 1 */
76:Core/Src/main.c ****
77:Core/Src/main.c **** /* MCU Configuration--------------------------------------------------------*/
78:Core/Src/main.c ****
79:Core/Src/main.c **** /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
80:Core/Src/main.c **** HAL_Init();
81:Core/Src/main.c ****
82:Core/Src/main.c **** /* USER CODE BEGIN Init */
83:Core/Src/main.c ****
84:Core/Src/main.c **** /* USER CODE END Init */
85:Core/Src/main.c ****
86:Core/Src/main.c **** /* Configure the system clock */
87:Core/Src/main.c **** SystemClock_Config();
88:Core/Src/main.c ****
89:Core/Src/main.c **** /* USER CODE BEGIN SysInit */
90:Core/Src/main.c ****
ARM GAS /tmp/ccZ9xwps.s page 3
91:Core/Src/main.c **** /* USER CODE END SysInit */
92:Core/Src/main.c ****
93:Core/Src/main.c **** /* Initialize all configured peripherals */
94:Core/Src/main.c **** MX_GPIO_Init();
95:Core/Src/main.c **** MX_CAN_Init();
96:Core/Src/main.c **** /* USER CODE BEGIN 2 */
97:Core/Src/main.c **** // Pull the Output enable low to activate TS3USB221
98:Core/Src/main.c **** GPIOA->ODR &= !PIN_USB_NOT_OE;
99:Core/Src/main.c ****
100:Core/Src/main.c **** /* USER CODE END 2 */
101:Core/Src/main.c ****
102:Core/Src/main.c **** /* Infinite loop */
103:Core/Src/main.c **** /* USER CODE BEGIN WHILE */
104:Core/Src/main.c **** while (1)
105:Core/Src/main.c **** {
106:Core/Src/main.c **** /* USER CODE END WHILE */
107:Core/Src/main.c ****
108:Core/Src/main.c **** /* USER CODE BEGIN 3 */
109:Core/Src/main.c **** // Enable USB Power
110:Core/Src/main.c **** GPIOA->ODR ^= PIN_RELAY_USB;
111:Core/Src/main.c **** // First apply Power to give the slave device time to init
112:Core/Src/main.c **** HAL_Delay(200);;
113:Core/Src/main.c **** GPIOA->ODR ^= PIN_USB_S;
114:Core/Src/main.c **** GPIOA->ODR ^= PIN_USER_LED;
115:Core/Src/main.c ****
116:Core/Src/main.c **** HAL_Delay(10000);
117:Core/Src/main.c **** }
118:Core/Src/main.c **** /* USER CODE END 3 */
119:Core/Src/main.c **** }
120:Core/Src/main.c ****
121:Core/Src/main.c **** /**
122:Core/Src/main.c **** * @brief System Clock Configuration
123:Core/Src/main.c **** * @retval None
124:Core/Src/main.c **** */
125:Core/Src/main.c **** void SystemClock_Config(void)
126:Core/Src/main.c **** {
127:Core/Src/main.c **** RCC_OscInitTypeDef RCC_OscInitStruct = {0};
128:Core/Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
129:Core/Src/main.c ****
130:Core/Src/main.c **** /** Initializes the RCC Oscillators according to the specified parameters
131:Core/Src/main.c **** * in the RCC_OscInitTypeDef structure.
132:Core/Src/main.c **** */
133:Core/Src/main.c **** RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
134:Core/Src/main.c **** RCC_OscInitStruct.HSEState = RCC_HSE_ON;
135:Core/Src/main.c **** RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
136:Core/Src/main.c **** RCC_OscInitStruct.HSIState = RCC_HSI_ON;
137:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
138:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
139:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
140:Core/Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
141:Core/Src/main.c **** {
142:Core/Src/main.c **** Error_Handler();
143:Core/Src/main.c **** }
144:Core/Src/main.c **** /** Initializes the CPU, AHB and APB buses clocks
145:Core/Src/main.c **** */
146:Core/Src/main.c **** RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
147:Core/Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
ARM GAS /tmp/ccZ9xwps.s page 4
148:Core/Src/main.c **** RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
149:Core/Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
150:Core/Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
151:Core/Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
152:Core/Src/main.c ****
153:Core/Src/main.c **** if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
154:Core/Src/main.c **** {
155:Core/Src/main.c **** Error_Handler();
156:Core/Src/main.c **** }
157:Core/Src/main.c **** }
158:Core/Src/main.c ****
159:Core/Src/main.c **** /**
160:Core/Src/main.c **** * @brief CAN Initialization Function
161:Core/Src/main.c **** * @param None
162:Core/Src/main.c **** * @retval None
163:Core/Src/main.c **** */
164:Core/Src/main.c **** static void MX_CAN_Init(void)
165:Core/Src/main.c **** {
166:Core/Src/main.c ****
167:Core/Src/main.c **** /* USER CODE BEGIN CAN_Init 0 */
168:Core/Src/main.c ****
169:Core/Src/main.c **** /* USER CODE END CAN_Init 0 */
170:Core/Src/main.c ****
171:Core/Src/main.c **** /* USER CODE BEGIN CAN_Init 1 */
172:Core/Src/main.c ****
173:Core/Src/main.c **** /* USER CODE END CAN_Init 1 */
174:Core/Src/main.c **** hcan.Instance = CAN1;
175:Core/Src/main.c **** hcan.Init.Prescaler = 16;
176:Core/Src/main.c **** hcan.Init.Mode = CAN_MODE_NORMAL;
177:Core/Src/main.c **** hcan.Init.SyncJumpWidth = CAN_SJW_1TQ;
178:Core/Src/main.c **** hcan.Init.TimeSeg1 = CAN_BS1_1TQ;
179:Core/Src/main.c **** hcan.Init.TimeSeg2 = CAN_BS2_1TQ;
180:Core/Src/main.c **** hcan.Init.TimeTriggeredMode = DISABLE;
181:Core/Src/main.c **** hcan.Init.AutoBusOff = DISABLE;
182:Core/Src/main.c **** hcan.Init.AutoWakeUp = DISABLE;
183:Core/Src/main.c **** hcan.Init.AutoRetransmission = DISABLE;
184:Core/Src/main.c **** hcan.Init.ReceiveFifoLocked = DISABLE;
185:Core/Src/main.c **** hcan.Init.TransmitFifoPriority = DISABLE;
186:Core/Src/main.c **** if (HAL_CAN_Init(&hcan) != HAL_OK)
187:Core/Src/main.c **** {
188:Core/Src/main.c **** Error_Handler();
189:Core/Src/main.c **** }
190:Core/Src/main.c **** /* USER CODE BEGIN CAN_Init 2 */
191:Core/Src/main.c ****
192:Core/Src/main.c **** /* USER CODE END CAN_Init 2 */
193:Core/Src/main.c ****
194:Core/Src/main.c **** }
195:Core/Src/main.c ****
196:Core/Src/main.c **** /**
197:Core/Src/main.c **** * @brief GPIO Initialization Function
198:Core/Src/main.c **** * @param None
199:Core/Src/main.c **** * @retval None
200:Core/Src/main.c **** */
201:Core/Src/main.c **** static void MX_GPIO_Init(void)
202:Core/Src/main.c **** {
26 .loc 1 202 1 view -0
27 .cfi_startproc
ARM GAS /tmp/ccZ9xwps.s page 5
28 @ args = 0, pretend = 0, frame = 32
29 @ frame_needed = 0, uses_anonymous_args = 0
30 0000 30B5 push {r4, r5, lr}
31 .LCFI0:
32 .cfi_def_cfa_offset 12
33 .cfi_offset 4, -12
34 .cfi_offset 5, -8
35 .cfi_offset 14, -4
36 0002 89B0 sub sp, sp, #36
37 .LCFI1:
38 .cfi_def_cfa_offset 48
203:Core/Src/main.c **** GPIO_InitTypeDef GPIO_InitStruct = {0};
39 .loc 1 203 3 view .LVU1
40 .loc 1 203 20 is_stmt 0 view .LVU2
41 0004 0024 movs r4, #0
42 0006 0494 str r4, [sp, #16]
43 0008 0594 str r4, [sp, #20]
44 000a 0694 str r4, [sp, #24]
45 000c 0794 str r4, [sp, #28]
204:Core/Src/main.c ****
205:Core/Src/main.c **** /* GPIO Ports Clock Enable */
206:Core/Src/main.c **** __HAL_RCC_GPIOD_CLK_ENABLE();
46 .loc 1 206 3 is_stmt 1 view .LVU3
47 .LBB2:
48 .loc 1 206 3 view .LVU4
49 .loc 1 206 3 view .LVU5
50 000e 174B ldr r3, .L3
51 0010 9A69 ldr r2, [r3, #24]
52 0012 42F02002 orr r2, r2, #32
53 0016 9A61 str r2, [r3, #24]
54 .loc 1 206 3 view .LVU6
55 0018 9A69 ldr r2, [r3, #24]
56 001a 02F02002 and r2, r2, #32
57 001e 0192 str r2, [sp, #4]
58 .loc 1 206 3 view .LVU7
59 0020 019A ldr r2, [sp, #4]
60 .LBE2:
207:Core/Src/main.c **** __HAL_RCC_GPIOA_CLK_ENABLE();
61 .loc 1 207 3 view .LVU8
62 .LBB3:
63 .loc 1 207 3 view .LVU9
64 .loc 1 207 3 view .LVU10
65 0022 9A69 ldr r2, [r3, #24]
66 0024 42F00402 orr r2, r2, #4
67 0028 9A61 str r2, [r3, #24]
68 .loc 1 207 3 view .LVU11
69 002a 9A69 ldr r2, [r3, #24]
70 002c 02F00402 and r2, r2, #4
71 0030 0292 str r2, [sp, #8]
72 .loc 1 207 3 view .LVU12
73 0032 029A ldr r2, [sp, #8]
74 .LBE3:
208:Core/Src/main.c **** __HAL_RCC_GPIOB_CLK_ENABLE();
75 .loc 1 208 3 view .LVU13
76 .LBB4:
77 .loc 1 208 3 view .LVU14
78 .loc 1 208 3 view .LVU15
ARM GAS /tmp/ccZ9xwps.s page 6
79 0034 9A69 ldr r2, [r3, #24]
80 0036 42F00802 orr r2, r2, #8
81 003a 9A61 str r2, [r3, #24]
82 .loc 1 208 3 view .LVU16
83 003c 9B69 ldr r3, [r3, #24]
84 003e 03F00803 and r3, r3, #8
85 0042 0393 str r3, [sp, #12]
86 .loc 1 208 3 view .LVU17
87 0044 039B ldr r3, [sp, #12]
88 .LBE4:
209:Core/Src/main.c ****
210:Core/Src/main.c **** /*Configure GPIO pin Output Level */
211:Core/Src/main.c **** HAL_GPIO_WritePin(GPIOA, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3
89 .loc 1 211 3 view .LVU18
90 0046 0A4D ldr r5, .L3+4
91 0048 2246 mov r2, r4
92 004a 1F21 movs r1, #31
93 004c 2846 mov r0, r5
94 004e FFF7FEFF bl HAL_GPIO_WritePin
95 .LVL0:
212:Core/Src/main.c **** |GPIO_PIN_4, GPIO_PIN_RESET);
213:Core/Src/main.c ****
214:Core/Src/main.c **** /*Configure GPIO pins : PA0 PA1 PA2 PA3
215:Core/Src/main.c **** PA4 */
216:Core/Src/main.c **** GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3
96 .loc 1 216 3 view .LVU19
97 .loc 1 216 23 is_stmt 0 view .LVU20
98 0052 1F23 movs r3, #31
99 0054 0493 str r3, [sp, #16]
217:Core/Src/main.c **** |GPIO_PIN_4;
218:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
100 .loc 1 218 3 is_stmt 1 view .LVU21
101 .loc 1 218 24 is_stmt 0 view .LVU22
102 0056 0123 movs r3, #1
103 0058 0593 str r3, [sp, #20]
219:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
104 .loc 1 219 3 is_stmt 1 view .LVU23
105 .loc 1 219 24 is_stmt 0 view .LVU24
106 005a 0694 str r4, [sp, #24]
220:Core/Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
107 .loc 1 220 3 is_stmt 1 view .LVU25
108 .loc 1 220 25 is_stmt 0 view .LVU26
109 005c 0223 movs r3, #2
110 005e 0793 str r3, [sp, #28]
221:Core/Src/main.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
111 .loc 1 221 3 is_stmt 1 view .LVU27
112 0060 04A9 add r1, sp, #16
113 0062 2846 mov r0, r5
114 0064 FFF7FEFF bl HAL_GPIO_Init
115 .LVL1:
222:Core/Src/main.c ****
223:Core/Src/main.c **** }
116 .loc 1 223 1 is_stmt 0 view .LVU28
117 0068 09B0 add sp, sp, #36
118 .LCFI2:
119 .cfi_def_cfa_offset 12
120 @ sp needed
ARM GAS /tmp/ccZ9xwps.s page 7
121 006a 30BD pop {r4, r5, pc}
122 .L4:
123 .align 2
124 .L3:
125 006c 00100240 .word 1073876992
126 0070 00080140 .word 1073809408
127 .cfi_endproc
128 .LFE68:
130 .section .text.MX_CAN_Init,"ax",%progbits
131 .align 1
132 .syntax unified
133 .thumb
134 .thumb_func
135 .fpu softvfp
137 MX_CAN_Init:
138 .LFB67:
165:Core/Src/main.c ****
139 .loc 1 165 1 is_stmt 1 view -0
140 .cfi_startproc
141 @ args = 0, pretend = 0, frame = 0
142 @ frame_needed = 0, uses_anonymous_args = 0
143 0000 08B5 push {r3, lr}
144 .LCFI3:
145 .cfi_def_cfa_offset 8
146 .cfi_offset 3, -8
147 .cfi_offset 14, -4
174:Core/Src/main.c **** hcan.Init.Prescaler = 16;
148 .loc 1 174 3 view .LVU30
174:Core/Src/main.c **** hcan.Init.Prescaler = 16;
149 .loc 1 174 17 is_stmt 0 view .LVU31
150 0002 0948 ldr r0, .L7
151 0004 094B ldr r3, .L7+4
152 0006 0360 str r3, [r0]
175:Core/Src/main.c **** hcan.Init.Mode = CAN_MODE_NORMAL;
153 .loc 1 175 3 is_stmt 1 view .LVU32
175:Core/Src/main.c **** hcan.Init.Mode = CAN_MODE_NORMAL;
154 .loc 1 175 23 is_stmt 0 view .LVU33
155 0008 1023 movs r3, #16
156 000a 4360 str r3, [r0, #4]
176:Core/Src/main.c **** hcan.Init.SyncJumpWidth = CAN_SJW_1TQ;
157 .loc 1 176 3 is_stmt 1 view .LVU34
176:Core/Src/main.c **** hcan.Init.SyncJumpWidth = CAN_SJW_1TQ;
158 .loc 1 176 18 is_stmt 0 view .LVU35
159 000c 0023 movs r3, #0
160 000e 8360 str r3, [r0, #8]
177:Core/Src/main.c **** hcan.Init.TimeSeg1 = CAN_BS1_1TQ;
161 .loc 1 177 3 is_stmt 1 view .LVU36
177:Core/Src/main.c **** hcan.Init.TimeSeg1 = CAN_BS1_1TQ;
162 .loc 1 177 27 is_stmt 0 view .LVU37
163 0010 C360 str r3, [r0, #12]
178:Core/Src/main.c **** hcan.Init.TimeSeg2 = CAN_BS2_1TQ;
164 .loc 1 178 3 is_stmt 1 view .LVU38
178:Core/Src/main.c **** hcan.Init.TimeSeg2 = CAN_BS2_1TQ;
165 .loc 1 178 22 is_stmt 0 view .LVU39
166 0012 0361 str r3, [r0, #16]
179:Core/Src/main.c **** hcan.Init.TimeTriggeredMode = DISABLE;
167 .loc 1 179 3 is_stmt 1 view .LVU40
ARM GAS /tmp/ccZ9xwps.s page 8
179:Core/Src/main.c **** hcan.Init.TimeTriggeredMode = DISABLE;
168 .loc 1 179 22 is_stmt 0 view .LVU41
169 0014 4361 str r3, [r0, #20]
180:Core/Src/main.c **** hcan.Init.AutoBusOff = DISABLE;
170 .loc 1 180 3 is_stmt 1 view .LVU42
180:Core/Src/main.c **** hcan.Init.AutoBusOff = DISABLE;
171 .loc 1 180 31 is_stmt 0 view .LVU43
172 0016 0376 strb r3, [r0, #24]
181:Core/Src/main.c **** hcan.Init.AutoWakeUp = DISABLE;
173 .loc 1 181 3 is_stmt 1 view .LVU44
181:Core/Src/main.c **** hcan.Init.AutoWakeUp = DISABLE;
174 .loc 1 181 24 is_stmt 0 view .LVU45
175 0018 4376 strb r3, [r0, #25]
182:Core/Src/main.c **** hcan.Init.AutoRetransmission = DISABLE;
176 .loc 1 182 3 is_stmt 1 view .LVU46
182:Core/Src/main.c **** hcan.Init.AutoRetransmission = DISABLE;
177 .loc 1 182 24 is_stmt 0 view .LVU47
178 001a 8376 strb r3, [r0, #26]
183:Core/Src/main.c **** hcan.Init.ReceiveFifoLocked = DISABLE;
179 .loc 1 183 3 is_stmt 1 view .LVU48
183:Core/Src/main.c **** hcan.Init.ReceiveFifoLocked = DISABLE;
180 .loc 1 183 32 is_stmt 0 view .LVU49
181 001c C376 strb r3, [r0, #27]
184:Core/Src/main.c **** hcan.Init.TransmitFifoPriority = DISABLE;
182 .loc 1 184 3 is_stmt 1 view .LVU50
184:Core/Src/main.c **** hcan.Init.TransmitFifoPriority = DISABLE;
183 .loc 1 184 31 is_stmt 0 view .LVU51
184 001e 0377 strb r3, [r0, #28]
185:Core/Src/main.c **** if (HAL_CAN_Init(&hcan) != HAL_OK)
185 .loc 1 185 3 is_stmt 1 view .LVU52
185:Core/Src/main.c **** if (HAL_CAN_Init(&hcan) != HAL_OK)
186 .loc 1 185 34 is_stmt 0 view .LVU53
187 0020 4377 strb r3, [r0, #29]
186:Core/Src/main.c **** {
188 .loc 1 186 3 is_stmt 1 view .LVU54
186:Core/Src/main.c **** {
189 .loc 1 186 7 is_stmt 0 view .LVU55
190 0022 FFF7FEFF bl HAL_CAN_Init
191 .LVL2:
194:Core/Src/main.c ****
192 .loc 1 194 1 view .LVU56
193 0026 08BD pop {r3, pc}
194 .L8:
195 .align 2
196 .L7:
197 0028 00000000 .word hcan
198 002c 00640040 .word 1073767424
199 .cfi_endproc
200 .LFE67:
202 .section .text.SystemClock_Config,"ax",%progbits
203 .align 1
204 .global SystemClock_Config
205 .syntax unified
206 .thumb
207 .thumb_func
208 .fpu softvfp
210 SystemClock_Config:
ARM GAS /tmp/ccZ9xwps.s page 9
211 .LFB66:
126:Core/Src/main.c **** RCC_OscInitTypeDef RCC_OscInitStruct = {0};
212 .loc 1 126 1 is_stmt 1 view -0
213 .cfi_startproc
214 @ args = 0, pretend = 0, frame = 64
215 @ frame_needed = 0, uses_anonymous_args = 0
216 0000 70B5 push {r4, r5, r6, lr}
217 .LCFI4:
218 .cfi_def_cfa_offset 16
219 .cfi_offset 4, -16
220 .cfi_offset 5, -12
221 .cfi_offset 6, -8
222 .cfi_offset 14, -4
223 0002 90B0 sub sp, sp, #64
224 .LCFI5:
225 .cfi_def_cfa_offset 80
127:Core/Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
226 .loc 1 127 3 view .LVU58
127:Core/Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
227 .loc 1 127 22 is_stmt 0 view .LVU59
228 0004 0024 movs r4, #0
229 0006 0894 str r4, [sp, #32]
230 0008 0994 str r4, [sp, #36]
231 000a 0B94 str r4, [sp, #44]
232 000c 0C94 str r4, [sp, #48]
128:Core/Src/main.c ****
233 .loc 1 128 3 is_stmt 1 view .LVU60
128:Core/Src/main.c ****
234 .loc 1 128 22 is_stmt 0 view .LVU61
235 000e 0194 str r4, [sp, #4]
236 0010 0294 str r4, [sp, #8]
237 0012 0394 str r4, [sp, #12]
238 0014 0494 str r4, [sp, #16]
239 0016 0594 str r4, [sp, #20]
133:Core/Src/main.c **** RCC_OscInitStruct.HSEState = RCC_HSE_ON;
240 .loc 1 133 3 is_stmt 1 view .LVU62
133:Core/Src/main.c **** RCC_OscInitStruct.HSEState = RCC_HSE_ON;
241 .loc 1 133 36 is_stmt 0 view .LVU63
242 0018 0125 movs r5, #1
243 001a 0695 str r5, [sp, #24]
134:Core/Src/main.c **** RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
244 .loc 1 134 3 is_stmt 1 view .LVU64
134:Core/Src/main.c **** RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
245 .loc 1 134 30 is_stmt 0 view .LVU65
246 001c 4FF48033 mov r3, #65536
247 0020 0793 str r3, [sp, #28]
135:Core/Src/main.c **** RCC_OscInitStruct.HSIState = RCC_HSI_ON;
248 .loc 1 135 3 is_stmt 1 view .LVU66
136:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
249 .loc 1 136 3 view .LVU67
136:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
250 .loc 1 136 30 is_stmt 0 view .LVU68
251 0022 0A95 str r5, [sp, #40]
137:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
252 .loc 1 137 3 is_stmt 1 view .LVU69
137:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
253 .loc 1 137 34 is_stmt 0 view .LVU70
ARM GAS /tmp/ccZ9xwps.s page 10
254 0024 0226 movs r6, #2
255 0026 0D96 str r6, [sp, #52]
138:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
256 .loc 1 138 3 is_stmt 1 view .LVU71
138:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
257 .loc 1 138 35 is_stmt 0 view .LVU72
258 0028 0E93 str r3, [sp, #56]
139:Core/Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
259 .loc 1 139 3 is_stmt 1 view .LVU73
139:Core/Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
260 .loc 1 139 32 is_stmt 0 view .LVU74
261 002a 4FF4E013 mov r3, #1835008
262 002e 0F93 str r3, [sp, #60]
140:Core/Src/main.c **** {
263 .loc 1 140 3 is_stmt 1 view .LVU75
140:Core/Src/main.c **** {
264 .loc 1 140 7 is_stmt 0 view .LVU76
265 0030 06A8 add r0, sp, #24
266 0032 FFF7FEFF bl HAL_RCC_OscConfig
267 .LVL3:
146:Core/Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
268 .loc 1 146 3 is_stmt 1 view .LVU77
146:Core/Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
269 .loc 1 146 31 is_stmt 0 view .LVU78
270 0036 0F23 movs r3, #15
271 0038 0193 str r3, [sp, #4]
148:Core/Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
272 .loc 1 148 3 is_stmt 1 view .LVU79
148:Core/Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
273 .loc 1 148 34 is_stmt 0 view .LVU80
274 003a 0296 str r6, [sp, #8]
149:Core/Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
275 .loc 1 149 3 is_stmt 1 view .LVU81
149:Core/Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
276 .loc 1 149 35 is_stmt 0 view .LVU82
277 003c 0394 str r4, [sp, #12]
150:Core/Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
278 .loc 1 150 3 is_stmt 1 view .LVU83
150:Core/Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
279 .loc 1 150 36 is_stmt 0 view .LVU84
280 003e 0494 str r4, [sp, #16]
151:Core/Src/main.c ****
281 .loc 1 151 3 is_stmt 1 view .LVU85
151:Core/Src/main.c ****
282 .loc 1 151 36 is_stmt 0 view .LVU86
283 0040 0594 str r4, [sp, #20]
153:Core/Src/main.c **** {
284 .loc 1 153 3 is_stmt 1 view .LVU87
153:Core/Src/main.c **** {
285 .loc 1 153 7 is_stmt 0 view .LVU88
286 0042 2946 mov r1, r5
287 0044 01A8 add r0, sp, #4
288 0046 FFF7FEFF bl HAL_RCC_ClockConfig
289 .LVL4:
157:Core/Src/main.c ****
290 .loc 1 157 1 view .LVU89
291 004a 10B0 add sp, sp, #64
ARM GAS /tmp/ccZ9xwps.s page 11
292 .LCFI6:
293 .cfi_def_cfa_offset 16
294 @ sp needed
295 004c 70BD pop {r4, r5, r6, pc}
296 .cfi_endproc
297 .LFE66:
299 .section .text.main,"ax",%progbits
300 .align 1
301 .global main
302 .syntax unified
303 .thumb
304 .thumb_func
305 .fpu softvfp
307 main:
308 .LFB65:
72:Core/Src/main.c **** /* USER CODE BEGIN 1 */
309 .loc 1 72 1 is_stmt 1 view -0
310 .cfi_startproc
311 @ Volatile: function does not return.
312 @ args = 0, pretend = 0, frame = 0
313 @ frame_needed = 0, uses_anonymous_args = 0
314 0000 08B5 push {r3, lr}
315 .LCFI7:
316 .cfi_def_cfa_offset 8
317 .cfi_offset 3, -8
318 .cfi_offset 14, -4
80:Core/Src/main.c ****
319 .loc 1 80 3 view .LVU91
320 0002 FFF7FEFF bl HAL_Init
321 .LVL5:
87:Core/Src/main.c ****
322 .loc 1 87 3 view .LVU92
323 0006 FFF7FEFF bl SystemClock_Config
324 .LVL6:
94:Core/Src/main.c **** MX_CAN_Init();
325 .loc 1 94 3 view .LVU93
326 000a FFF7FEFF bl MX_GPIO_Init
327 .LVL7:
95:Core/Src/main.c **** /* USER CODE BEGIN 2 */
328 .loc 1 95 3 view .LVU94
329 000e FFF7FEFF bl MX_CAN_Init
330 .LVL8:
98:Core/Src/main.c ****
331 .loc 1 98 3 view .LVU95
98:Core/Src/main.c ****
332 .loc 1 98 14 is_stmt 0 view .LVU96
333 0012 0C4B ldr r3, .L14
334 0014 DA68 ldr r2, [r3, #12]
335 0016 0022 movs r2, #0
336 0018 DA60 str r2, [r3, #12]
337 .L12:
104:Core/Src/main.c **** {
338 .loc 1 104 3 is_stmt 1 discriminator 1 view .LVU97
110:Core/Src/main.c **** // First apply Power to give the slave device time to init
339 .loc 1 110 5 discriminator 1 view .LVU98
110:Core/Src/main.c **** // First apply Power to give the slave device time to init
340 .loc 1 110 16 is_stmt 0 discriminator 1 view .LVU99
ARM GAS /tmp/ccZ9xwps.s page 12
341 001a 0A4C ldr r4, .L14
342 001c E368 ldr r3, [r4, #12]
343 001e 83F00103 eor r3, r3, #1
344 0022 E360 str r3, [r4, #12]
112:Core/Src/main.c **** GPIOA->ODR ^= PIN_USB_S;
345 .loc 1 112 5 is_stmt 1 discriminator 1 view .LVU100
346 0024 C820 movs r0, #200
347 0026 FFF7FEFF bl HAL_Delay
348 .LVL9:
112:Core/Src/main.c **** GPIOA->ODR ^= PIN_USB_S;
349 .loc 1 112 20 discriminator 1 view .LVU101
113:Core/Src/main.c **** GPIOA->ODR ^= PIN_USER_LED;
350 .loc 1 113 5 discriminator 1 view .LVU102
113:Core/Src/main.c **** GPIOA->ODR ^= PIN_USER_LED;
351 .loc 1 113 16 is_stmt 0 discriminator 1 view .LVU103
352 002a E368 ldr r3, [r4, #12]
353 002c 83F00803 eor r3, r3, #8
354 0030 E360 str r3, [r4, #12]
114:Core/Src/main.c ****
355 .loc 1 114 5 is_stmt 1 discriminator 1 view .LVU104
114:Core/Src/main.c ****
356 .loc 1 114 16 is_stmt 0 discriminator 1 view .LVU105
357 0032 E368 ldr r3, [r4, #12]
358 0034 83F01003 eor r3, r3, #16
359 0038 E360 str r3, [r4, #12]
116:Core/Src/main.c **** }
360 .loc 1 116 5 is_stmt 1 discriminator 1 view .LVU106
361 003a 42F21070 movw r0, #10000
362 003e FFF7FEFF bl HAL_Delay
363 .LVL10:
364 0042 EAE7 b .L12
365 .L15:
366 .align 2
367 .L14:
368 0044 00080140 .word 1073809408
369 .cfi_endproc
370 .LFE65:
372 .section .text.Error_Handler,"ax",%progbits
373 .align 1
374 .global Error_Handler
375 .syntax unified
376 .thumb
377 .thumb_func
378 .fpu softvfp
380 Error_Handler:
381 .LFB69:
224:Core/Src/main.c ****
225:Core/Src/main.c **** /* USER CODE BEGIN 4 */
226:Core/Src/main.c ****
227:Core/Src/main.c **** /* USER CODE END 4 */
228:Core/Src/main.c ****
229:Core/Src/main.c **** /**
230:Core/Src/main.c **** * @brief This function is executed in case of error occurrence.
231:Core/Src/main.c **** * @retval None
232:Core/Src/main.c **** */
233:Core/Src/main.c **** void Error_Handler(void)
234:Core/Src/main.c **** {
ARM GAS /tmp/ccZ9xwps.s page 13
382 .loc 1 234 1 view -0
383 .cfi_startproc
384 @ args = 0, pretend = 0, frame = 0
385 @ frame_needed = 0, uses_anonymous_args = 0
386 @ link register save eliminated.
235:Core/Src/main.c **** /* USER CODE BEGIN Error_Handler_Debug */
236:Core/Src/main.c **** /* User can add his own implementation to report the HAL error return state */
237:Core/Src/main.c ****
238:Core/Src/main.c **** /* USER CODE END Error_Handler_Debug */
239:Core/Src/main.c **** }
387 .loc 1 239 1 view .LVU108
388 0000 7047 bx lr
389 .cfi_endproc
390 .LFE69:
392 .comm hcan,40,4
393 .text
394 .Letext0:
395 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h"
396 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h"
397 .file 4 "Drivers/CMSIS/Include/core_cm3.h"
398 .file 5 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h"
399 .file 6 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h"
400 .file 7 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h"
401 .file 8 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h"
402 .file 9 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h"
403 .file 10 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h"
404 .file 11 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h"
405 .file 12 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h"
406 .file 13 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h"
ARM GAS /tmp/ccZ9xwps.s page 14
DEFINED SYMBOLS
*ABS*:0000000000000000 main.c
/tmp/ccZ9xwps.s:16 .text.MX_GPIO_Init:0000000000000000 $t
/tmp/ccZ9xwps.s:23 .text.MX_GPIO_Init:0000000000000000 MX_GPIO_Init
/tmp/ccZ9xwps.s:125 .text.MX_GPIO_Init:000000000000006c $d
/tmp/ccZ9xwps.s:131 .text.MX_CAN_Init:0000000000000000 $t
/tmp/ccZ9xwps.s:137 .text.MX_CAN_Init:0000000000000000 MX_CAN_Init
/tmp/ccZ9xwps.s:197 .text.MX_CAN_Init:0000000000000028 $d
*COM*:0000000000000028 hcan
/tmp/ccZ9xwps.s:203 .text.SystemClock_Config:0000000000000000 $t
/tmp/ccZ9xwps.s:210 .text.SystemClock_Config:0000000000000000 SystemClock_Config
/tmp/ccZ9xwps.s:300 .text.main:0000000000000000 $t
/tmp/ccZ9xwps.s:307 .text.main:0000000000000000 main
/tmp/ccZ9xwps.s:368 .text.main:0000000000000044 $d
/tmp/ccZ9xwps.s:373 .text.Error_Handler:0000000000000000 $t
/tmp/ccZ9xwps.s:380 .text.Error_Handler:0000000000000000 Error_Handler
UNDEFINED SYMBOLS
HAL_GPIO_WritePin
HAL_GPIO_Init
HAL_CAN_Init
HAL_RCC_OscConfig
HAL_RCC_ClockConfig
HAL_Init
HAL_Delay

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Drivers/CMSIS/Include/cmsis_compiler.h:
Drivers/CMSIS/Include/cmsis_gcc.h:
Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h:
Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h:

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build/stm32f1xx_hal_dma.o: \
Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h \
Core/Inc/stm32f1xx_hal_conf.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h \
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h \
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h \
Drivers/CMSIS/Include/core_cm3.h Drivers/CMSIS/Include/cmsis_version.h \
Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h \
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Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h:
Core/Inc/stm32f1xx_hal_conf.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h:
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h:
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h:
Drivers/CMSIS/Include/core_cm3.h:
Drivers/CMSIS/Include/cmsis_version.h:
Drivers/CMSIS/Include/cmsis_compiler.h:
Drivers/CMSIS/Include/cmsis_gcc.h:
Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h:
Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h:
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build/stm32f1xx_hal_exti.o: \
Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h \
Core/Inc/stm32f1xx_hal_conf.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h \
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h \
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h \
Drivers/CMSIS/Include/core_cm3.h Drivers/CMSIS/Include/cmsis_version.h \
Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h \
Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h:
Core/Inc/stm32f1xx_hal_conf.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h:
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h:
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h:
Drivers/CMSIS/Include/core_cm3.h:
Drivers/CMSIS/Include/cmsis_version.h:
Drivers/CMSIS/Include/cmsis_compiler.h:
Drivers/CMSIS/Include/cmsis_gcc.h:
Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h:
Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h:

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build/stm32f1xx_hal_flash.o: \
Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h \
Core/Inc/stm32f1xx_hal_conf.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h \
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h \
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h \
Drivers/CMSIS/Include/core_cm3.h Drivers/CMSIS/Include/cmsis_version.h \
Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h \
Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h:
Core/Inc/stm32f1xx_hal_conf.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h:
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h:
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h:
Drivers/CMSIS/Include/core_cm3.h:
Drivers/CMSIS/Include/cmsis_version.h:
Drivers/CMSIS/Include/cmsis_compiler.h:
Drivers/CMSIS/Include/cmsis_gcc.h:
Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h:
Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h:

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build/stm32f1xx_hal_flash_ex.o: \
Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h \
Core/Inc/stm32f1xx_hal_conf.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h \
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h \
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h \
Drivers/CMSIS/Include/core_cm3.h Drivers/CMSIS/Include/cmsis_version.h \
Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h \
Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h:
Core/Inc/stm32f1xx_hal_conf.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h:
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h:
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h:
Drivers/CMSIS/Include/core_cm3.h:
Drivers/CMSIS/Include/cmsis_version.h:
Drivers/CMSIS/Include/cmsis_compiler.h:
Drivers/CMSIS/Include/cmsis_gcc.h:
Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h:
Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h:

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build/stm32f1xx_hal_gpio.o: \
Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h \
Core/Inc/stm32f1xx_hal_conf.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h \
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h \
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h \
Drivers/CMSIS/Include/core_cm3.h Drivers/CMSIS/Include/cmsis_version.h \
Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h \
Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h:
Core/Inc/stm32f1xx_hal_conf.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h:
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h:
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h:
Drivers/CMSIS/Include/core_cm3.h:
Drivers/CMSIS/Include/cmsis_version.h:
Drivers/CMSIS/Include/cmsis_compiler.h:
Drivers/CMSIS/Include/cmsis_gcc.h:
Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h:
Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h:

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build/stm32f1xx_hal_gpio_ex.o: \
Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h \
Core/Inc/stm32f1xx_hal_conf.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h \
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h \
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h \
Drivers/CMSIS/Include/core_cm3.h Drivers/CMSIS/Include/cmsis_version.h \
Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h \
Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h:
Core/Inc/stm32f1xx_hal_conf.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h:
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h:
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h:
Drivers/CMSIS/Include/core_cm3.h:
Drivers/CMSIS/Include/cmsis_version.h:
Drivers/CMSIS/Include/cmsis_compiler.h:
Drivers/CMSIS/Include/cmsis_gcc.h:
Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h:
Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h:

247
rusci-firmware/build/stm32f1xx_hal_gpio_ex.lst Normal file
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@@ -0,0 +1,247 @@
ARM GAS /tmp/ccDLntp7.s page 1
1 .cpu cortex-m3
2 .eabi_attribute 20, 1
3 .eabi_attribute 21, 1
4 .eabi_attribute 23, 3
5 .eabi_attribute 24, 1
6 .eabi_attribute 25, 1
7 .eabi_attribute 26, 1
8 .eabi_attribute 30, 1
9 .eabi_attribute 34, 1
10 .eabi_attribute 18, 4
11 .file "stm32f1xx_hal_gpio_ex.c"
12 .text
13 .Ltext0:
14 .cfi_sections .debug_frame
15 .section .text.HAL_GPIOEx_ConfigEventout,"ax",%progbits
16 .align 1
17 .global HAL_GPIOEx_ConfigEventout
18 .arch armv7-m
19 .syntax unified
20 .thumb
21 .thumb_func
22 .fpu softvfp
24 HAL_GPIOEx_ConfigEventout:
25 .LVL0:
26 .LFB65:
27 .file 1 "Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c"
1:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** /**
2:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** ******************************************************************************
3:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** * @file stm32f1xx_hal_gpio_ex.c
4:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** * @author MCD Application Team
5:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** * @brief GPIO Extension HAL module driver.
6:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** * This file provides firmware functions to manage the following
7:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** * functionalities of the General Purpose Input/Output (GPIO) extension peripheral.
8:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** * + Extended features functions
9:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** *
10:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** @verbatim
11:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** ==============================================================================
12:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** ##### GPIO Peripheral extension features #####
13:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** ==============================================================================
14:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** [..] GPIO module on STM32F1 family, manage also the AFIO register:
15:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** (+) Possibility to use the EVENTOUT Cortex feature
16:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c ****
17:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** ##### How to use this driver #####
18:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** ==============================================================================
19:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** [..] This driver provides functions to use EVENTOUT Cortex feature
20:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** (#) Configure EVENTOUT Cortex feature using the function HAL_GPIOEx_ConfigEventout()
21:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** (#) Activate EVENTOUT Cortex feature using the HAL_GPIOEx_EnableEventout()
22:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** (#) Deactivate EVENTOUT Cortex feature using the HAL_GPIOEx_DisableEventout()
23:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c ****
24:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** @endverbatim
25:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** ******************************************************************************
26:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** * @attention
27:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** *
28:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
29:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** * All rights reserved.</center></h2>
30:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** *
31:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** * This software component is licensed by ST under BSD 3-Clause license,
ARM GAS /tmp/ccDLntp7.s page 2
32:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** * the "License"; You may not use this file except in compliance with the
33:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** * License. You may obtain a copy of the License at:
34:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** * opensource.org/licenses/BSD-3-Clause
35:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** *
36:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** ******************************************************************************
37:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** */
38:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c ****
39:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** /* Includes ------------------------------------------------------------------*/
40:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** #include "stm32f1xx_hal.h"
41:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c ****
42:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** /** @addtogroup STM32F1xx_HAL_Driver
43:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** * @{
44:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** */
45:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c ****
46:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** /** @defgroup GPIOEx GPIOEx
47:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** * @brief GPIO HAL module driver
48:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** * @{
49:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** */
50:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c ****
51:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** #ifdef HAL_GPIO_MODULE_ENABLED
52:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c ****
53:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** /** @defgroup GPIOEx_Exported_Functions GPIOEx Exported Functions
54:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** * @{
55:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** */
56:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c ****
57:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** /** @defgroup GPIOEx_Exported_Functions_Group1 Extended features functions
58:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** * @brief Extended features functions
59:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** *
60:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** @verbatim
61:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** ==============================================================================
62:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** ##### Extended features functions #####
63:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** ==============================================================================
64:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** [..] This section provides functions allowing to:
65:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** (+) Configure EVENTOUT Cortex feature using the function HAL_GPIOEx_ConfigEventout()
66:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** (+) Activate EVENTOUT Cortex feature using the HAL_GPIOEx_EnableEventout()
67:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** (+) Deactivate EVENTOUT Cortex feature using the HAL_GPIOEx_DisableEventout()
68:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c ****
69:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** @endverbatim
70:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** * @{
71:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** */
72:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c ****
73:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** /**
74:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** * @brief Configures the port and pin on which the EVENTOUT Cortex signal will be connected.
75:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** * @param GPIO_PortSource Select the port used to output the Cortex EVENTOUT signal.
76:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** * This parameter can be a value of @ref GPIOEx_EVENTOUT_PORT.
77:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** * @param GPIO_PinSource Select the pin used to output the Cortex EVENTOUT signal.
78:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** * This parameter can be a value of @ref GPIOEx_EVENTOUT_PIN.
79:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** * @retval None
80:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** */
81:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** void HAL_GPIOEx_ConfigEventout(uint32_t GPIO_PortSource, uint32_t GPIO_PinSource)
82:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** {
28 .loc 1 82 1 view -0
29 .cfi_startproc
30 @ args = 0, pretend = 0, frame = 0
31 @ frame_needed = 0, uses_anonymous_args = 0
32 @ link register save eliminated.
83:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** /* Verify the parameters */
ARM GAS /tmp/ccDLntp7.s page 3
84:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** assert_param(IS_AFIO_EVENTOUT_PORT(GPIO_PortSource));
33 .loc 1 84 3 view .LVU1
85:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** assert_param(IS_AFIO_EVENTOUT_PIN(GPIO_PinSource));
34 .loc 1 85 3 view .LVU2
86:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c ****
87:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** /* Apply the new configuration */
88:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** MODIFY_REG(AFIO->EVCR, (AFIO_EVCR_PORT) | (AFIO_EVCR_PIN), (GPIO_PortSource) | (GPIO_PinSource));
35 .loc 1 88 3 view .LVU3
36 0000 034A ldr r2, .L2
37 0002 1368 ldr r3, [r2]
38 0004 23F07F03 bic r3, r3, #127
39 0008 0143 orrs r1, r1, r0
40 .LVL1:
41 .loc 1 88 3 is_stmt 0 view .LVU4
42 000a 0B43 orrs r3, r3, r1
43 000c 1360 str r3, [r2]
89:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** }
44 .loc 1 89 1 view .LVU5
45 000e 7047 bx lr
46 .L3:
47 .align 2
48 .L2:
49 0010 00000140 .word 1073807360
50 .cfi_endproc
51 .LFE65:
53 .section .text.HAL_GPIOEx_EnableEventout,"ax",%progbits
54 .align 1
55 .global HAL_GPIOEx_EnableEventout
56 .syntax unified
57 .thumb
58 .thumb_func
59 .fpu softvfp
61 HAL_GPIOEx_EnableEventout:
62 .LFB66:
90:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c ****
91:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** /**
92:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** * @brief Enables the Event Output.
93:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** * @retval None
94:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** */
95:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** void HAL_GPIOEx_EnableEventout(void)
96:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** {
63 .loc 1 96 1 is_stmt 1 view -0
64 .cfi_startproc
65 @ args = 0, pretend = 0, frame = 0
66 @ frame_needed = 0, uses_anonymous_args = 0
67 @ link register save eliminated.
97:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** SET_BIT(AFIO->EVCR, AFIO_EVCR_EVOE);
68 .loc 1 97 3 view .LVU7
69 0000 024A ldr r2, .L5
70 0002 1368 ldr r3, [r2]
71 0004 43F08003 orr r3, r3, #128
72 0008 1360 str r3, [r2]
98:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** }
73 .loc 1 98 1 is_stmt 0 view .LVU8
74 000a 7047 bx lr
75 .L6:
76 .align 2
ARM GAS /tmp/ccDLntp7.s page 4
77 .L5:
78 000c 00000140 .word 1073807360
79 .cfi_endproc
80 .LFE66:
82 .section .text.HAL_GPIOEx_DisableEventout,"ax",%progbits
83 .align 1
84 .global HAL_GPIOEx_DisableEventout
85 .syntax unified
86 .thumb
87 .thumb_func
88 .fpu softvfp
90 HAL_GPIOEx_DisableEventout:
91 .LFB67:
99:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c ****
100:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** /**
101:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** * @brief Disables the Event Output.
102:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** * @retval None
103:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** */
104:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** void HAL_GPIOEx_DisableEventout(void)
105:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** {
92 .loc 1 105 1 is_stmt 1 view -0
93 .cfi_startproc
94 @ args = 0, pretend = 0, frame = 0
95 @ frame_needed = 0, uses_anonymous_args = 0
96 @ link register save eliminated.
106:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** CLEAR_BIT(AFIO->EVCR, AFIO_EVCR_EVOE);
97 .loc 1 106 3 view .LVU10
98 0000 024A ldr r2, .L8
99 0002 1368 ldr r3, [r2]
100 0004 23F08003 bic r3, r3, #128
101 0008 1360 str r3, [r2]
107:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c **** }
102 .loc 1 107 1 is_stmt 0 view .LVU11
103 000a 7047 bx lr
104 .L9:
105 .align 2
106 .L8:
107 000c 00000140 .word 1073807360
108 .cfi_endproc
109 .LFE67:
111 .text
112 .Letext0:
113 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h"
114 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h"
115 .file 4 "Drivers/CMSIS/Include/core_cm3.h"
116 .file 5 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h"
117 .file 6 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h"
118 .file 7 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h"
ARM GAS /tmp/ccDLntp7.s page 5
DEFINED SYMBOLS
*ABS*:0000000000000000 stm32f1xx_hal_gpio_ex.c
/tmp/ccDLntp7.s:16 .text.HAL_GPIOEx_ConfigEventout:0000000000000000 $t
/tmp/ccDLntp7.s:24 .text.HAL_GPIOEx_ConfigEventout:0000000000000000 HAL_GPIOEx_ConfigEventout
/tmp/ccDLntp7.s:49 .text.HAL_GPIOEx_ConfigEventout:0000000000000010 $d
/tmp/ccDLntp7.s:54 .text.HAL_GPIOEx_EnableEventout:0000000000000000 $t
/tmp/ccDLntp7.s:61 .text.HAL_GPIOEx_EnableEventout:0000000000000000 HAL_GPIOEx_EnableEventout
/tmp/ccDLntp7.s:78 .text.HAL_GPIOEx_EnableEventout:000000000000000c $d
/tmp/ccDLntp7.s:83 .text.HAL_GPIOEx_DisableEventout:0000000000000000 $t
/tmp/ccDLntp7.s:90 .text.HAL_GPIOEx_DisableEventout:0000000000000000 HAL_GPIOEx_DisableEventout
/tmp/ccDLntp7.s:107 .text.HAL_GPIOEx_DisableEventout:000000000000000c $d
NO UNDEFINED SYMBOLS

BIN
rusci-firmware/build/stm32f1xx_hal_gpio_ex.o Normal file
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70
rusci-firmware/build/stm32f1xx_hal_msp.d Normal file
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build/stm32f1xx_hal_msp.o: Core/Src/stm32f1xx_hal_msp.c Core/Inc/main.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h \
Core/Inc/stm32f1xx_hal_conf.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h \
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h \
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h \
Drivers/CMSIS/Include/core_cm3.h Drivers/CMSIS/Include/cmsis_version.h \
Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h \
Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h
Core/Inc/main.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h:
Core/Inc/stm32f1xx_hal_conf.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h:
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h:
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h:
Drivers/CMSIS/Include/core_cm3.h:
Drivers/CMSIS/Include/cmsis_version.h:
Drivers/CMSIS/Include/cmsis_compiler.h:
Drivers/CMSIS/Include/cmsis_gcc.h:
Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h:
Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h:

525
rusci-firmware/build/stm32f1xx_hal_msp.lst Normal file
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ARM GAS /tmp/ccEGCTiT.s page 1
1 .cpu cortex-m3
2 .eabi_attribute 20, 1
3 .eabi_attribute 21, 1
4 .eabi_attribute 23, 3
5 .eabi_attribute 24, 1
6 .eabi_attribute 25, 1
7 .eabi_attribute 26, 1
8 .eabi_attribute 30, 1
9 .eabi_attribute 34, 1
10 .eabi_attribute 18, 4
11 .file "stm32f1xx_hal_msp.c"
12 .text
13 .Ltext0:
14 .cfi_sections .debug_frame
15 .section .text.HAL_MspInit,"ax",%progbits
16 .align 1
17 .global HAL_MspInit
18 .arch armv7-m
19 .syntax unified
20 .thumb
21 .thumb_func
22 .fpu softvfp
24 HAL_MspInit:
25 .LFB65:
26 .file 1 "Core/Src/stm32f1xx_hal_msp.c"
1:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN Header */
2:Core/Src/stm32f1xx_hal_msp.c **** /**
3:Core/Src/stm32f1xx_hal_msp.c **** ******************************************************************************
4:Core/Src/stm32f1xx_hal_msp.c **** * File Name : stm32f1xx_hal_msp.c
5:Core/Src/stm32f1xx_hal_msp.c **** * Description : This file provides code for the MSP Initialization
6:Core/Src/stm32f1xx_hal_msp.c **** * and de-Initialization codes.
7:Core/Src/stm32f1xx_hal_msp.c **** ******************************************************************************
8:Core/Src/stm32f1xx_hal_msp.c **** * @attention
9:Core/Src/stm32f1xx_hal_msp.c **** *
10:Core/Src/stm32f1xx_hal_msp.c **** * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
11:Core/Src/stm32f1xx_hal_msp.c **** * All rights reserved.</center></h2>
12:Core/Src/stm32f1xx_hal_msp.c **** *
13:Core/Src/stm32f1xx_hal_msp.c **** * This software component is licensed by ST under BSD 3-Clause license,
14:Core/Src/stm32f1xx_hal_msp.c **** * the "License"; You may not use this file except in compliance with the
15:Core/Src/stm32f1xx_hal_msp.c **** * License. You may obtain a copy of the License at:
16:Core/Src/stm32f1xx_hal_msp.c **** * opensource.org/licenses/BSD-3-Clause
17:Core/Src/stm32f1xx_hal_msp.c **** *
18:Core/Src/stm32f1xx_hal_msp.c **** ******************************************************************************
19:Core/Src/stm32f1xx_hal_msp.c **** */
20:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END Header */
21:Core/Src/stm32f1xx_hal_msp.c ****
22:Core/Src/stm32f1xx_hal_msp.c **** /* Includes ------------------------------------------------------------------*/
23:Core/Src/stm32f1xx_hal_msp.c **** #include "main.h"
24:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN Includes */
25:Core/Src/stm32f1xx_hal_msp.c ****
26:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END Includes */
27:Core/Src/stm32f1xx_hal_msp.c ****
28:Core/Src/stm32f1xx_hal_msp.c **** /* Private typedef -----------------------------------------------------------*/
29:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN TD */
30:Core/Src/stm32f1xx_hal_msp.c ****
31:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END TD */
32:Core/Src/stm32f1xx_hal_msp.c ****
ARM GAS /tmp/ccEGCTiT.s page 2
33:Core/Src/stm32f1xx_hal_msp.c **** /* Private define ------------------------------------------------------------*/
34:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN Define */
35:Core/Src/stm32f1xx_hal_msp.c ****
36:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END Define */
37:Core/Src/stm32f1xx_hal_msp.c ****
38:Core/Src/stm32f1xx_hal_msp.c **** /* Private macro -------------------------------------------------------------*/
39:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN Macro */
40:Core/Src/stm32f1xx_hal_msp.c ****
41:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END Macro */
42:Core/Src/stm32f1xx_hal_msp.c ****
43:Core/Src/stm32f1xx_hal_msp.c **** /* Private variables ---------------------------------------------------------*/
44:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN PV */
45:Core/Src/stm32f1xx_hal_msp.c ****
46:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END PV */
47:Core/Src/stm32f1xx_hal_msp.c ****
48:Core/Src/stm32f1xx_hal_msp.c **** /* Private function prototypes -----------------------------------------------*/
49:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN PFP */
50:Core/Src/stm32f1xx_hal_msp.c ****
51:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END PFP */
52:Core/Src/stm32f1xx_hal_msp.c ****
53:Core/Src/stm32f1xx_hal_msp.c **** /* External functions --------------------------------------------------------*/
54:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN ExternalFunctions */
55:Core/Src/stm32f1xx_hal_msp.c ****
56:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END ExternalFunctions */
57:Core/Src/stm32f1xx_hal_msp.c ****
58:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN 0 */
59:Core/Src/stm32f1xx_hal_msp.c ****
60:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END 0 */
61:Core/Src/stm32f1xx_hal_msp.c **** /**
62:Core/Src/stm32f1xx_hal_msp.c **** * Initializes the Global MSP.
63:Core/Src/stm32f1xx_hal_msp.c **** */
64:Core/Src/stm32f1xx_hal_msp.c **** void HAL_MspInit(void)
65:Core/Src/stm32f1xx_hal_msp.c **** {
27 .loc 1 65 1 view -0
28 .cfi_startproc
29 @ args = 0, pretend = 0, frame = 8
30 @ frame_needed = 0, uses_anonymous_args = 0
31 @ link register save eliminated.
32 0000 82B0 sub sp, sp, #8
33 .LCFI0:
34 .cfi_def_cfa_offset 8
66:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN MspInit 0 */
67:Core/Src/stm32f1xx_hal_msp.c ****
68:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END MspInit 0 */
69:Core/Src/stm32f1xx_hal_msp.c ****
70:Core/Src/stm32f1xx_hal_msp.c **** __HAL_RCC_AFIO_CLK_ENABLE();
35 .loc 1 70 3 view .LVU1
36 .LBB2:
37 .loc 1 70 3 view .LVU2
38 .loc 1 70 3 view .LVU3
39 0002 0E4B ldr r3, .L3
40 0004 9A69 ldr r2, [r3, #24]
41 0006 42F00102 orr r2, r2, #1
42 000a 9A61 str r2, [r3, #24]
43 .loc 1 70 3 view .LVU4
44 000c 9A69 ldr r2, [r3, #24]
45 000e 02F00102 and r2, r2, #1
ARM GAS /tmp/ccEGCTiT.s page 3
46 0012 0092 str r2, [sp]
47 .loc 1 70 3 view .LVU5
48 0014 009A ldr r2, [sp]
49 .LBE2:
71:Core/Src/stm32f1xx_hal_msp.c **** __HAL_RCC_PWR_CLK_ENABLE();
50 .loc 1 71 3 view .LVU6
51 .LBB3:
52 .loc 1 71 3 view .LVU7
53 .loc 1 71 3 view .LVU8
54 0016 DA69 ldr r2, [r3, #28]
55 0018 42F08052 orr r2, r2, #268435456
56 001c DA61 str r2, [r3, #28]
57 .loc 1 71 3 view .LVU9
58 001e DB69 ldr r3, [r3, #28]
59 0020 03F08053 and r3, r3, #268435456
60 0024 0193 str r3, [sp, #4]
61 .loc 1 71 3 view .LVU10
62 0026 019B ldr r3, [sp, #4]
63 .LBE3:
72:Core/Src/stm32f1xx_hal_msp.c ****
73:Core/Src/stm32f1xx_hal_msp.c **** /* System interrupt init*/
74:Core/Src/stm32f1xx_hal_msp.c ****
75:Core/Src/stm32f1xx_hal_msp.c **** /** DISABLE: JTAG-DP Disabled and SW-DP Disabled
76:Core/Src/stm32f1xx_hal_msp.c **** */
77:Core/Src/stm32f1xx_hal_msp.c **** __HAL_AFIO_REMAP_SWJ_DISABLE();
64 .loc 1 77 3 view .LVU11
65 .LBB4:
66 .loc 1 77 3 view .LVU12
67 0028 054A ldr r2, .L3+4
68 002a 5368 ldr r3, [r2, #4]
69 .LVL0:
70 .loc 1 77 3 view .LVU13
71 002c 23F0E063 bic r3, r3, #117440512
72 .LVL1:
73 .loc 1 77 3 view .LVU14
74 0030 43F08063 orr r3, r3, #67108864
75 .LVL2:
76 .loc 1 77 3 view .LVU15
77 0034 5360 str r3, [r2, #4]
78 .LBE4:
78:Core/Src/stm32f1xx_hal_msp.c ****
79:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN MspInit 1 */
80:Core/Src/stm32f1xx_hal_msp.c ****
81:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END MspInit 1 */
82:Core/Src/stm32f1xx_hal_msp.c **** }
79 .loc 1 82 1 is_stmt 0 view .LVU16
80 0036 02B0 add sp, sp, #8
81 .LCFI1:
82 .cfi_def_cfa_offset 0
83 @ sp needed
84 0038 7047 bx lr
85 .L4:
86 003a 00BF .align 2
87 .L3:
88 003c 00100240 .word 1073876992
89 0040 00000140 .word 1073807360
90 .cfi_endproc
ARM GAS /tmp/ccEGCTiT.s page 4
91 .LFE65:
93 .section .text.HAL_CAN_MspInit,"ax",%progbits
94 .align 1
95 .global HAL_CAN_MspInit
96 .syntax unified
97 .thumb
98 .thumb_func
99 .fpu softvfp
101 HAL_CAN_MspInit:
102 .LVL3:
103 .LFB66:
83:Core/Src/stm32f1xx_hal_msp.c ****
84:Core/Src/stm32f1xx_hal_msp.c **** /**
85:Core/Src/stm32f1xx_hal_msp.c **** * @brief CAN MSP Initialization
86:Core/Src/stm32f1xx_hal_msp.c **** * This function configures the hardware resources used in this example
87:Core/Src/stm32f1xx_hal_msp.c **** * @param hcan: CAN handle pointer
88:Core/Src/stm32f1xx_hal_msp.c **** * @retval None
89:Core/Src/stm32f1xx_hal_msp.c **** */
90:Core/Src/stm32f1xx_hal_msp.c **** void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
91:Core/Src/stm32f1xx_hal_msp.c **** {
104 .loc 1 91 1 is_stmt 1 view -0
105 .cfi_startproc
106 @ args = 0, pretend = 0, frame = 24
107 @ frame_needed = 0, uses_anonymous_args = 0
108 .loc 1 91 1 is_stmt 0 view .LVU18
109 0000 10B5 push {r4, lr}
110 .LCFI2:
111 .cfi_def_cfa_offset 8
112 .cfi_offset 4, -8
113 .cfi_offset 14, -4
114 0002 86B0 sub sp, sp, #24
115 .LCFI3:
116 .cfi_def_cfa_offset 32
92:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitTypeDef GPIO_InitStruct = {0};
117 .loc 1 92 3 is_stmt 1 view .LVU19
118 .loc 1 92 20 is_stmt 0 view .LVU20
119 0004 0023 movs r3, #0
120 0006 0293 str r3, [sp, #8]
121 0008 0393 str r3, [sp, #12]
122 000a 0493 str r3, [sp, #16]
123 000c 0593 str r3, [sp, #20]
93:Core/Src/stm32f1xx_hal_msp.c **** if(hcan->Instance==CAN1)
124 .loc 1 93 3 is_stmt 1 view .LVU21
125 .loc 1 93 10 is_stmt 0 view .LVU22
126 000e 0268 ldr r2, [r0]
127 .loc 1 93 5 view .LVU23
128 0010 1A4B ldr r3, .L9
129 0012 9A42 cmp r2, r3
130 0014 01D0 beq .L8
131 .LVL4:
132 .L5:
94:Core/Src/stm32f1xx_hal_msp.c **** {
95:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN CAN1_MspInit 0 */
96:Core/Src/stm32f1xx_hal_msp.c ****
97:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END CAN1_MspInit 0 */
98:Core/Src/stm32f1xx_hal_msp.c **** /* Peripheral clock enable */
99:Core/Src/stm32f1xx_hal_msp.c **** __HAL_RCC_CAN1_CLK_ENABLE();
ARM GAS /tmp/ccEGCTiT.s page 5
100:Core/Src/stm32f1xx_hal_msp.c ****
101:Core/Src/stm32f1xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE();
102:Core/Src/stm32f1xx_hal_msp.c **** /**CAN GPIO Configuration
103:Core/Src/stm32f1xx_hal_msp.c **** PB8 ------> CAN_RX
104:Core/Src/stm32f1xx_hal_msp.c **** PB9 ------> CAN_TX
105:Core/Src/stm32f1xx_hal_msp.c **** */
106:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Pin = GPIO_PIN_8;
107:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
108:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
109:Core/Src/stm32f1xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
110:Core/Src/stm32f1xx_hal_msp.c ****
111:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Pin = GPIO_PIN_9;
112:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
113:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
114:Core/Src/stm32f1xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
115:Core/Src/stm32f1xx_hal_msp.c ****
116:Core/Src/stm32f1xx_hal_msp.c **** __HAL_AFIO_REMAP_CAN1_2();
117:Core/Src/stm32f1xx_hal_msp.c ****
118:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN CAN1_MspInit 1 */
119:Core/Src/stm32f1xx_hal_msp.c ****
120:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END CAN1_MspInit 1 */
121:Core/Src/stm32f1xx_hal_msp.c **** }
122:Core/Src/stm32f1xx_hal_msp.c ****
123:Core/Src/stm32f1xx_hal_msp.c **** }
133 .loc 1 123 1 view .LVU24
134 0016 06B0 add sp, sp, #24
135 .LCFI4:
136 .cfi_remember_state
137 .cfi_def_cfa_offset 8
138 @ sp needed
139 0018 10BD pop {r4, pc}
140 .LVL5:
141 .L8:
142 .LCFI5:
143 .cfi_restore_state
99:Core/Src/stm32f1xx_hal_msp.c ****
144 .loc 1 99 5 is_stmt 1 view .LVU25
145 .LBB5:
99:Core/Src/stm32f1xx_hal_msp.c ****
146 .loc 1 99 5 view .LVU26
99:Core/Src/stm32f1xx_hal_msp.c ****
147 .loc 1 99 5 view .LVU27
148 001a 03F5D633 add r3, r3, #109568
149 001e DA69 ldr r2, [r3, #28]
150 0020 42F00072 orr r2, r2, #33554432
151 0024 DA61 str r2, [r3, #28]
99:Core/Src/stm32f1xx_hal_msp.c ****
152 .loc 1 99 5 view .LVU28
153 0026 DA69 ldr r2, [r3, #28]
154 0028 02F00072 and r2, r2, #33554432
155 002c 0092 str r2, [sp]
99:Core/Src/stm32f1xx_hal_msp.c ****
156 .loc 1 99 5 view .LVU29
157 002e 009A ldr r2, [sp]
158 .LBE5:
101:Core/Src/stm32f1xx_hal_msp.c **** /**CAN GPIO Configuration
159 .loc 1 101 5 view .LVU30
ARM GAS /tmp/ccEGCTiT.s page 6
160 .LBB6:
101:Core/Src/stm32f1xx_hal_msp.c **** /**CAN GPIO Configuration
161 .loc 1 101 5 view .LVU31
101:Core/Src/stm32f1xx_hal_msp.c **** /**CAN GPIO Configuration
162 .loc 1 101 5 view .LVU32
163 0030 9A69 ldr r2, [r3, #24]
164 0032 42F00802 orr r2, r2, #8
165 0036 9A61 str r2, [r3, #24]
101:Core/Src/stm32f1xx_hal_msp.c **** /**CAN GPIO Configuration
166 .loc 1 101 5 view .LVU33
167 0038 9B69 ldr r3, [r3, #24]
168 003a 03F00803 and r3, r3, #8
169 003e 0193 str r3, [sp, #4]
101:Core/Src/stm32f1xx_hal_msp.c **** /**CAN GPIO Configuration
170 .loc 1 101 5 view .LVU34
171 0040 019B ldr r3, [sp, #4]
172 .LBE6:
106:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
173 .loc 1 106 5 view .LVU35
106:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
174 .loc 1 106 25 is_stmt 0 view .LVU36
175 0042 4FF48073 mov r3, #256
176 0046 0293 str r3, [sp, #8]
107:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
177 .loc 1 107 5 is_stmt 1 view .LVU37
108:Core/Src/stm32f1xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
178 .loc 1 108 5 view .LVU38
109:Core/Src/stm32f1xx_hal_msp.c ****
179 .loc 1 109 5 view .LVU39
180 0048 0D4C ldr r4, .L9+4
181 004a 02A9 add r1, sp, #8
182 004c 2046 mov r0, r4
183 .LVL6:
109:Core/Src/stm32f1xx_hal_msp.c ****
184 .loc 1 109 5 is_stmt 0 view .LVU40
185 004e FFF7FEFF bl HAL_GPIO_Init
186 .LVL7:
111:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
187 .loc 1 111 5 is_stmt 1 view .LVU41
111:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
188 .loc 1 111 25 is_stmt 0 view .LVU42
189 0052 4FF40073 mov r3, #512
190 0056 0293 str r3, [sp, #8]
112:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
191 .loc 1 112 5 is_stmt 1 view .LVU43
112:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
192 .loc 1 112 26 is_stmt 0 view .LVU44
193 0058 0223 movs r3, #2
194 005a 0393 str r3, [sp, #12]
113:Core/Src/stm32f1xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
195 .loc 1 113 5 is_stmt 1 view .LVU45
113:Core/Src/stm32f1xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
196 .loc 1 113 27 is_stmt 0 view .LVU46
197 005c 0323 movs r3, #3
198 005e 0593 str r3, [sp, #20]
114:Core/Src/stm32f1xx_hal_msp.c ****
199 .loc 1 114 5 is_stmt 1 view .LVU47
ARM GAS /tmp/ccEGCTiT.s page 7
200 0060 02A9 add r1, sp, #8
201 0062 2046 mov r0, r4
202 0064 FFF7FEFF bl HAL_GPIO_Init
203 .LVL8:
116:Core/Src/stm32f1xx_hal_msp.c ****
204 .loc 1 116 5 view .LVU48
205 .LBB7:
116:Core/Src/stm32f1xx_hal_msp.c ****
206 .loc 1 116 5 view .LVU49
207 0068 064A ldr r2, .L9+8
208 006a 5368 ldr r3, [r2, #4]
209 .LVL9:
116:Core/Src/stm32f1xx_hal_msp.c ****
210 .loc 1 116 5 view .LVU50
211 006c 23F4C043 bic r3, r3, #24576
212 .LVL10:
116:Core/Src/stm32f1xx_hal_msp.c ****
213 .loc 1 116 5 view .LVU51
116:Core/Src/stm32f1xx_hal_msp.c ****
214 .loc 1 116 5 view .LVU52
215 0070 43F0E063 orr r3, r3, #117440512
216 .LVL11:
116:Core/Src/stm32f1xx_hal_msp.c ****
217 .loc 1 116 5 is_stmt 0 view .LVU53
218 0074 43F48043 orr r3, r3, #16384
219 .LVL12:
116:Core/Src/stm32f1xx_hal_msp.c ****
220 .loc 1 116 5 is_stmt 1 view .LVU54
221 0078 5360 str r3, [r2, #4]
222 .LBE7:
223 .loc 1 123 1 is_stmt 0 view .LVU55
224 007a CCE7 b .L5
225 .L10:
226 .align 2
227 .L9:
228 007c 00640040 .word 1073767424
229 0080 000C0140 .word 1073810432
230 0084 00000140 .word 1073807360
231 .cfi_endproc
232 .LFE66:
234 .section .text.HAL_CAN_MspDeInit,"ax",%progbits
235 .align 1
236 .global HAL_CAN_MspDeInit
237 .syntax unified
238 .thumb
239 .thumb_func
240 .fpu softvfp
242 HAL_CAN_MspDeInit:
243 .LVL13:
244 .LFB67:
124:Core/Src/stm32f1xx_hal_msp.c ****
125:Core/Src/stm32f1xx_hal_msp.c **** /**
126:Core/Src/stm32f1xx_hal_msp.c **** * @brief CAN MSP De-Initialization
127:Core/Src/stm32f1xx_hal_msp.c **** * This function freeze the hardware resources used in this example
128:Core/Src/stm32f1xx_hal_msp.c **** * @param hcan: CAN handle pointer
129:Core/Src/stm32f1xx_hal_msp.c **** * @retval None
130:Core/Src/stm32f1xx_hal_msp.c **** */
ARM GAS /tmp/ccEGCTiT.s page 8
131:Core/Src/stm32f1xx_hal_msp.c **** void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)
132:Core/Src/stm32f1xx_hal_msp.c **** {
245 .loc 1 132 1 is_stmt 1 view -0
246 .cfi_startproc
247 @ args = 0, pretend = 0, frame = 0
248 @ frame_needed = 0, uses_anonymous_args = 0
249 .loc 1 132 1 is_stmt 0 view .LVU57
250 0000 08B5 push {r3, lr}
251 .LCFI6:
252 .cfi_def_cfa_offset 8
253 .cfi_offset 3, -8
254 .cfi_offset 14, -4
133:Core/Src/stm32f1xx_hal_msp.c **** if(hcan->Instance==CAN1)
255 .loc 1 133 3 is_stmt 1 view .LVU58
256 .loc 1 133 10 is_stmt 0 view .LVU59
257 0002 0268 ldr r2, [r0]
258 .loc 1 133 5 view .LVU60
259 0004 074B ldr r3, .L15
260 0006 9A42 cmp r2, r3
261 0008 00D0 beq .L14
262 .LVL14:
263 .L11:
134:Core/Src/stm32f1xx_hal_msp.c **** {
135:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN CAN1_MspDeInit 0 */
136:Core/Src/stm32f1xx_hal_msp.c ****
137:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END CAN1_MspDeInit 0 */
138:Core/Src/stm32f1xx_hal_msp.c **** /* Peripheral clock disable */
139:Core/Src/stm32f1xx_hal_msp.c **** __HAL_RCC_CAN1_CLK_DISABLE();
140:Core/Src/stm32f1xx_hal_msp.c ****
141:Core/Src/stm32f1xx_hal_msp.c **** /**CAN GPIO Configuration
142:Core/Src/stm32f1xx_hal_msp.c **** PB8 ------> CAN_RX
143:Core/Src/stm32f1xx_hal_msp.c **** PB9 ------> CAN_TX
144:Core/Src/stm32f1xx_hal_msp.c **** */
145:Core/Src/stm32f1xx_hal_msp.c **** HAL_GPIO_DeInit(GPIOB, GPIO_PIN_8|GPIO_PIN_9);
146:Core/Src/stm32f1xx_hal_msp.c ****
147:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN CAN1_MspDeInit 1 */
148:Core/Src/stm32f1xx_hal_msp.c ****
149:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END CAN1_MspDeInit 1 */
150:Core/Src/stm32f1xx_hal_msp.c **** }
151:Core/Src/stm32f1xx_hal_msp.c ****
152:Core/Src/stm32f1xx_hal_msp.c **** }
264 .loc 1 152 1 view .LVU61
265 000a 08BD pop {r3, pc}
266 .LVL15:
267 .L14:
139:Core/Src/stm32f1xx_hal_msp.c ****
268 .loc 1 139 5 is_stmt 1 view .LVU62
269 000c 064A ldr r2, .L15+4
270 000e D369 ldr r3, [r2, #28]
271 0010 23F00073 bic r3, r3, #33554432
272 0014 D361 str r3, [r2, #28]
145:Core/Src/stm32f1xx_hal_msp.c ****
273 .loc 1 145 5 view .LVU63
274 0016 4FF44071 mov r1, #768
275 001a 0448 ldr r0, .L15+8
276 .LVL16:
145:Core/Src/stm32f1xx_hal_msp.c ****
ARM GAS /tmp/ccEGCTiT.s page 9
277 .loc 1 145 5 is_stmt 0 view .LVU64
278 001c FFF7FEFF bl HAL_GPIO_DeInit
279 .LVL17:
280 .loc 1 152 1 view .LVU65
281 0020 F3E7 b .L11
282 .L16:
283 0022 00BF .align 2
284 .L15:
285 0024 00640040 .word 1073767424
286 0028 00100240 .word 1073876992
287 002c 000C0140 .word 1073810432
288 .cfi_endproc
289 .LFE67:
291 .text
292 .Letext0:
293 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h"
294 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h"
295 .file 4 "Drivers/CMSIS/Include/core_cm3.h"
296 .file 5 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h"
297 .file 6 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h"
298 .file 7 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h"
299 .file 8 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h"
300 .file 9 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h"
301 .file 10 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h"
ARM GAS /tmp/ccEGCTiT.s page 10
DEFINED SYMBOLS
*ABS*:0000000000000000 stm32f1xx_hal_msp.c
/tmp/ccEGCTiT.s:16 .text.HAL_MspInit:0000000000000000 $t
/tmp/ccEGCTiT.s:24 .text.HAL_MspInit:0000000000000000 HAL_MspInit
/tmp/ccEGCTiT.s:88 .text.HAL_MspInit:000000000000003c $d
/tmp/ccEGCTiT.s:94 .text.HAL_CAN_MspInit:0000000000000000 $t
/tmp/ccEGCTiT.s:101 .text.HAL_CAN_MspInit:0000000000000000 HAL_CAN_MspInit
/tmp/ccEGCTiT.s:228 .text.HAL_CAN_MspInit:000000000000007c $d
/tmp/ccEGCTiT.s:235 .text.HAL_CAN_MspDeInit:0000000000000000 $t
/tmp/ccEGCTiT.s:242 .text.HAL_CAN_MspDeInit:0000000000000000 HAL_CAN_MspDeInit
/tmp/ccEGCTiT.s:285 .text.HAL_CAN_MspDeInit:0000000000000024 $d
UNDEFINED SYMBOLS
HAL_GPIO_Init
HAL_GPIO_DeInit

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build/stm32f1xx_hal_pwr.o: \
Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h \
Core/Inc/stm32f1xx_hal_conf.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h \
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h \
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h \
Drivers/CMSIS/Include/core_cm3.h Drivers/CMSIS/Include/cmsis_version.h \
Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h \
Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h:
Core/Inc/stm32f1xx_hal_conf.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h:
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h:
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h:
Drivers/CMSIS/Include/core_cm3.h:
Drivers/CMSIS/Include/cmsis_version.h:
Drivers/CMSIS/Include/cmsis_compiler.h:
Drivers/CMSIS/Include/cmsis_gcc.h:
Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h:
Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h:

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build/stm32f1xx_hal_rcc.o: \
Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h \
Core/Inc/stm32f1xx_hal_conf.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h \
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h \
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h \
Drivers/CMSIS/Include/core_cm3.h Drivers/CMSIS/Include/cmsis_version.h \
Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h \
Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h:
Core/Inc/stm32f1xx_hal_conf.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h:
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h:
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h:
Drivers/CMSIS/Include/core_cm3.h:
Drivers/CMSIS/Include/cmsis_version.h:
Drivers/CMSIS/Include/cmsis_compiler.h:
Drivers/CMSIS/Include/cmsis_gcc.h:
Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h:
Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h:

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build/stm32f1xx_hal_rcc_ex.o: \
Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h \
Core/Inc/stm32f1xx_hal_conf.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h \
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h \
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h \
Drivers/CMSIS/Include/core_cm3.h Drivers/CMSIS/Include/cmsis_version.h \
Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h \
Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h:
Core/Inc/stm32f1xx_hal_conf.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h:
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h:
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h:
Drivers/CMSIS/Include/core_cm3.h:
Drivers/CMSIS/Include/cmsis_version.h:
Drivers/CMSIS/Include/cmsis_compiler.h:
Drivers/CMSIS/Include/cmsis_gcc.h:
Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h:
Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h:

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build/stm32f1xx_hal_tim.o: \
Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h \
Core/Inc/stm32f1xx_hal_conf.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h \
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h \
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h \
Drivers/CMSIS/Include/core_cm3.h Drivers/CMSIS/Include/cmsis_version.h \
Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h \
Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h:
Core/Inc/stm32f1xx_hal_conf.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h:
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h:
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h:
Drivers/CMSIS/Include/core_cm3.h:
Drivers/CMSIS/Include/cmsis_version.h:
Drivers/CMSIS/Include/cmsis_compiler.h:
Drivers/CMSIS/Include/cmsis_gcc.h:
Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h:
Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h:

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ARM GAS /tmp/ccz48V0i.s page 1
1 .cpu cortex-m3
2 .eabi_attribute 20, 1
3 .eabi_attribute 21, 1
4 .eabi_attribute 23, 3
5 .eabi_attribute 24, 1
6 .eabi_attribute 25, 1
7 .eabi_attribute 26, 1
8 .eabi_attribute 30, 1
9 .eabi_attribute 34, 1
10 .eabi_attribute 18, 4
11 .file "stm32f1xx_hal_tim.c"
12 .text
13 .Ltext0:
14 .cfi_sections .debug_frame
15 .Letext0:
16 .file 1 "/usr/arm-none-eabi/include/machine/_default_types.h"
17 .file 2 "/usr/arm-none-eabi/include/sys/_stdint.h"
18 .file 3 "Drivers/CMSIS/Include/core_cm3.h"
19 .file 4 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h"
20 .file 5 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h"
ARM GAS /tmp/ccz48V0i.s page 2
DEFINED SYMBOLS
*ABS*:0000000000000000 stm32f1xx_hal_tim.c
NO UNDEFINED SYMBOLS

BIN
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build/stm32f1xx_hal_tim_ex.o: \
Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h \
Core/Inc/stm32f1xx_hal_conf.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h \
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h \
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h \
Drivers/CMSIS/Include/core_cm3.h Drivers/CMSIS/Include/cmsis_version.h \
Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h \
Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h:
Core/Inc/stm32f1xx_hal_conf.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h:
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h:
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h:
Drivers/CMSIS/Include/core_cm3.h:
Drivers/CMSIS/Include/cmsis_version.h:
Drivers/CMSIS/Include/cmsis_compiler.h:
Drivers/CMSIS/Include/cmsis_gcc.h:
Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h:
Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h:

30
rusci-firmware/build/stm32f1xx_hal_tim_ex.lst Normal file
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@@ -0,0 +1,30 @@
ARM GAS /tmp/ccVRgzYR.s page 1
1 .cpu cortex-m3
2 .eabi_attribute 20, 1
3 .eabi_attribute 21, 1
4 .eabi_attribute 23, 3
5 .eabi_attribute 24, 1
6 .eabi_attribute 25, 1
7 .eabi_attribute 26, 1
8 .eabi_attribute 30, 1
9 .eabi_attribute 34, 1
10 .eabi_attribute 18, 4
11 .file "stm32f1xx_hal_tim_ex.c"
12 .text
13 .Ltext0:
14 .cfi_sections .debug_frame
15 .Letext0:
16 .file 1 "/usr/arm-none-eabi/include/machine/_default_types.h"
17 .file 2 "/usr/arm-none-eabi/include/sys/_stdint.h"
18 .file 3 "Drivers/CMSIS/Include/core_cm3.h"
19 .file 4 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h"
20 .file 5 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h"
ARM GAS /tmp/ccVRgzYR.s page 2
DEFINED SYMBOLS
*ABS*:0000000000000000 stm32f1xx_hal_tim_ex.c
NO UNDEFINED SYMBOLS

BIN
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73
rusci-firmware/build/stm32f1xx_it.d Normal file
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build/stm32f1xx_it.o: Core/Src/stm32f1xx_it.c Core/Inc/main.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h \
Core/Inc/stm32f1xx_hal_conf.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h \
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h \
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h \
Drivers/CMSIS/Include/core_cm3.h Drivers/CMSIS/Include/cmsis_version.h \
Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h \
Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h \
Core/Inc/stm32f1xx_it.h
Core/Inc/main.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h:
Core/Inc/stm32f1xx_hal_conf.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h:
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h:
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h:
Drivers/CMSIS/Include/core_cm3.h:
Drivers/CMSIS/Include/cmsis_version.h:
Drivers/CMSIS/Include/cmsis_compiler.h:
Drivers/CMSIS/Include/cmsis_gcc.h:
Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h:
Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h:
Core/Inc/stm32f1xx_it.h:

442
rusci-firmware/build/stm32f1xx_it.lst Normal file
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ARM GAS /tmp/ccOMxQCE.s page 1
1 .cpu cortex-m3
2 .eabi_attribute 20, 1
3 .eabi_attribute 21, 1
4 .eabi_attribute 23, 3
5 .eabi_attribute 24, 1
6 .eabi_attribute 25, 1
7 .eabi_attribute 26, 1
8 .eabi_attribute 30, 1
9 .eabi_attribute 34, 1
10 .eabi_attribute 18, 4
11 .file "stm32f1xx_it.c"
12 .text
13 .Ltext0:
14 .cfi_sections .debug_frame
15 .section .text.NMI_Handler,"ax",%progbits
16 .align 1
17 .global NMI_Handler
18 .arch armv7-m
19 .syntax unified
20 .thumb
21 .thumb_func
22 .fpu softvfp
24 NMI_Handler:
25 .LFB65:
26 .file 1 "Core/Src/stm32f1xx_it.c"
1:Core/Src/stm32f1xx_it.c **** /* USER CODE BEGIN Header */
2:Core/Src/stm32f1xx_it.c **** /**
3:Core/Src/stm32f1xx_it.c **** ******************************************************************************
4:Core/Src/stm32f1xx_it.c **** * @file stm32f1xx_it.c
5:Core/Src/stm32f1xx_it.c **** * @brief Interrupt Service Routines.
6:Core/Src/stm32f1xx_it.c **** ******************************************************************************
7:Core/Src/stm32f1xx_it.c **** * @attention
8:Core/Src/stm32f1xx_it.c **** *
9:Core/Src/stm32f1xx_it.c **** * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
10:Core/Src/stm32f1xx_it.c **** * All rights reserved.</center></h2>
11:Core/Src/stm32f1xx_it.c **** *
12:Core/Src/stm32f1xx_it.c **** * This software component is licensed by ST under BSD 3-Clause license,
13:Core/Src/stm32f1xx_it.c **** * the "License"; You may not use this file except in compliance with the
14:Core/Src/stm32f1xx_it.c **** * License. You may obtain a copy of the License at:
15:Core/Src/stm32f1xx_it.c **** * opensource.org/licenses/BSD-3-Clause
16:Core/Src/stm32f1xx_it.c **** *
17:Core/Src/stm32f1xx_it.c **** ******************************************************************************
18:Core/Src/stm32f1xx_it.c **** */
19:Core/Src/stm32f1xx_it.c **** /* USER CODE END Header */
20:Core/Src/stm32f1xx_it.c ****
21:Core/Src/stm32f1xx_it.c **** /* Includes ------------------------------------------------------------------*/
22:Core/Src/stm32f1xx_it.c **** #include "main.h"
23:Core/Src/stm32f1xx_it.c **** #include "stm32f1xx_it.h"
24:Core/Src/stm32f1xx_it.c **** /* Private includes ----------------------------------------------------------*/
25:Core/Src/stm32f1xx_it.c **** /* USER CODE BEGIN Includes */
26:Core/Src/stm32f1xx_it.c **** /* USER CODE END Includes */
27:Core/Src/stm32f1xx_it.c ****
28:Core/Src/stm32f1xx_it.c **** /* Private typedef -----------------------------------------------------------*/
29:Core/Src/stm32f1xx_it.c **** /* USER CODE BEGIN TD */
30:Core/Src/stm32f1xx_it.c ****
31:Core/Src/stm32f1xx_it.c **** /* USER CODE END TD */
32:Core/Src/stm32f1xx_it.c ****
ARM GAS /tmp/ccOMxQCE.s page 2
33:Core/Src/stm32f1xx_it.c **** /* Private define ------------------------------------------------------------*/
34:Core/Src/stm32f1xx_it.c **** /* USER CODE BEGIN PD */
35:Core/Src/stm32f1xx_it.c ****
36:Core/Src/stm32f1xx_it.c **** /* USER CODE END PD */
37:Core/Src/stm32f1xx_it.c ****
38:Core/Src/stm32f1xx_it.c **** /* Private macro -------------------------------------------------------------*/
39:Core/Src/stm32f1xx_it.c **** /* USER CODE BEGIN PM */
40:Core/Src/stm32f1xx_it.c ****
41:Core/Src/stm32f1xx_it.c **** /* USER CODE END PM */
42:Core/Src/stm32f1xx_it.c ****
43:Core/Src/stm32f1xx_it.c **** /* Private variables ---------------------------------------------------------*/
44:Core/Src/stm32f1xx_it.c **** /* USER CODE BEGIN PV */
45:Core/Src/stm32f1xx_it.c ****
46:Core/Src/stm32f1xx_it.c **** /* USER CODE END PV */
47:Core/Src/stm32f1xx_it.c ****
48:Core/Src/stm32f1xx_it.c **** /* Private function prototypes -----------------------------------------------*/
49:Core/Src/stm32f1xx_it.c **** /* USER CODE BEGIN PFP */
50:Core/Src/stm32f1xx_it.c ****
51:Core/Src/stm32f1xx_it.c **** /* USER CODE END PFP */
52:Core/Src/stm32f1xx_it.c ****
53:Core/Src/stm32f1xx_it.c **** /* Private user code ---------------------------------------------------------*/
54:Core/Src/stm32f1xx_it.c **** /* USER CODE BEGIN 0 */
55:Core/Src/stm32f1xx_it.c ****
56:Core/Src/stm32f1xx_it.c **** /* USER CODE END 0 */
57:Core/Src/stm32f1xx_it.c ****
58:Core/Src/stm32f1xx_it.c **** /* External variables --------------------------------------------------------*/
59:Core/Src/stm32f1xx_it.c ****
60:Core/Src/stm32f1xx_it.c **** /* USER CODE BEGIN EV */
61:Core/Src/stm32f1xx_it.c ****
62:Core/Src/stm32f1xx_it.c **** /* USER CODE END EV */
63:Core/Src/stm32f1xx_it.c ****
64:Core/Src/stm32f1xx_it.c **** /******************************************************************************/
65:Core/Src/stm32f1xx_it.c **** /* Cortex-M3 Processor Interruption and Exception Handlers */
66:Core/Src/stm32f1xx_it.c **** /******************************************************************************/
67:Core/Src/stm32f1xx_it.c **** /**
68:Core/Src/stm32f1xx_it.c **** * @brief This function handles Non maskable interrupt.
69:Core/Src/stm32f1xx_it.c **** */
70:Core/Src/stm32f1xx_it.c **** void NMI_Handler(void)
71:Core/Src/stm32f1xx_it.c **** {
27 .loc 1 71 1 view -0
28 .cfi_startproc
29 @ args = 0, pretend = 0, frame = 0
30 @ frame_needed = 0, uses_anonymous_args = 0
31 @ link register save eliminated.
72:Core/Src/stm32f1xx_it.c **** /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
73:Core/Src/stm32f1xx_it.c ****
74:Core/Src/stm32f1xx_it.c **** /* USER CODE END NonMaskableInt_IRQn 0 */
75:Core/Src/stm32f1xx_it.c **** /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
76:Core/Src/stm32f1xx_it.c ****
77:Core/Src/stm32f1xx_it.c **** /* USER CODE END NonMaskableInt_IRQn 1 */
78:Core/Src/stm32f1xx_it.c **** }
32 .loc 1 78 1 view .LVU1
33 0000 7047 bx lr
34 .cfi_endproc
35 .LFE65:
37 .section .text.HardFault_Handler,"ax",%progbits
38 .align 1
ARM GAS /tmp/ccOMxQCE.s page 3
39 .global HardFault_Handler
40 .syntax unified
41 .thumb
42 .thumb_func
43 .fpu softvfp
45 HardFault_Handler:
46 .LFB66:
79:Core/Src/stm32f1xx_it.c ****
80:Core/Src/stm32f1xx_it.c **** /**
81:Core/Src/stm32f1xx_it.c **** * @brief This function handles Hard fault interrupt.
82:Core/Src/stm32f1xx_it.c **** */
83:Core/Src/stm32f1xx_it.c **** void HardFault_Handler(void)
84:Core/Src/stm32f1xx_it.c **** {
47 .loc 1 84 1 view -0
48 .cfi_startproc
49 @ Volatile: function does not return.
50 @ args = 0, pretend = 0, frame = 0
51 @ frame_needed = 0, uses_anonymous_args = 0
52 @ link register save eliminated.
53 .L3:
85:Core/Src/stm32f1xx_it.c **** /* USER CODE BEGIN HardFault_IRQn 0 */
86:Core/Src/stm32f1xx_it.c ****
87:Core/Src/stm32f1xx_it.c **** /* USER CODE END HardFault_IRQn 0 */
88:Core/Src/stm32f1xx_it.c **** while (1)
54 .loc 1 88 3 discriminator 1 view .LVU3
89:Core/Src/stm32f1xx_it.c **** {
90:Core/Src/stm32f1xx_it.c **** /* USER CODE BEGIN W1_HardFault_IRQn 0 */
91:Core/Src/stm32f1xx_it.c **** /* USER CODE END W1_HardFault_IRQn 0 */
92:Core/Src/stm32f1xx_it.c **** }
55 .loc 1 92 3 discriminator 1 view .LVU4
56 0000 FEE7 b .L3
57 .cfi_endproc
58 .LFE66:
60 .section .text.MemManage_Handler,"ax",%progbits
61 .align 1
62 .global MemManage_Handler
63 .syntax unified
64 .thumb
65 .thumb_func
66 .fpu softvfp
68 MemManage_Handler:
69 .LFB67:
93:Core/Src/stm32f1xx_it.c **** }
94:Core/Src/stm32f1xx_it.c ****
95:Core/Src/stm32f1xx_it.c **** /**
96:Core/Src/stm32f1xx_it.c **** * @brief This function handles Memory management fault.
97:Core/Src/stm32f1xx_it.c **** */
98:Core/Src/stm32f1xx_it.c **** void MemManage_Handler(void)
99:Core/Src/stm32f1xx_it.c **** {
70 .loc 1 99 1 view -0
71 .cfi_startproc
72 @ Volatile: function does not return.
73 @ args = 0, pretend = 0, frame = 0
74 @ frame_needed = 0, uses_anonymous_args = 0
75 @ link register save eliminated.
76 .L5:
100:Core/Src/stm32f1xx_it.c **** /* USER CODE BEGIN MemoryManagement_IRQn 0 */
ARM GAS /tmp/ccOMxQCE.s page 4
101:Core/Src/stm32f1xx_it.c ****
102:Core/Src/stm32f1xx_it.c **** /* USER CODE END MemoryManagement_IRQn 0 */
103:Core/Src/stm32f1xx_it.c **** while (1)
77 .loc 1 103 3 discriminator 1 view .LVU6
104:Core/Src/stm32f1xx_it.c **** {
105:Core/Src/stm32f1xx_it.c **** /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
106:Core/Src/stm32f1xx_it.c **** /* USER CODE END W1_MemoryManagement_IRQn 0 */
107:Core/Src/stm32f1xx_it.c **** }
78 .loc 1 107 3 discriminator 1 view .LVU7
79 0000 FEE7 b .L5
80 .cfi_endproc
81 .LFE67:
83 .section .text.BusFault_Handler,"ax",%progbits
84 .align 1
85 .global BusFault_Handler
86 .syntax unified
87 .thumb
88 .thumb_func
89 .fpu softvfp
91 BusFault_Handler:
92 .LFB68:
108:Core/Src/stm32f1xx_it.c **** }
109:Core/Src/stm32f1xx_it.c ****
110:Core/Src/stm32f1xx_it.c **** /**
111:Core/Src/stm32f1xx_it.c **** * @brief This function handles Prefetch fault, memory access fault.
112:Core/Src/stm32f1xx_it.c **** */
113:Core/Src/stm32f1xx_it.c **** void BusFault_Handler(void)
114:Core/Src/stm32f1xx_it.c **** {
93 .loc 1 114 1 view -0
94 .cfi_startproc
95 @ Volatile: function does not return.
96 @ args = 0, pretend = 0, frame = 0
97 @ frame_needed = 0, uses_anonymous_args = 0
98 @ link register save eliminated.
99 .L7:
115:Core/Src/stm32f1xx_it.c **** /* USER CODE BEGIN BusFault_IRQn 0 */
116:Core/Src/stm32f1xx_it.c ****
117:Core/Src/stm32f1xx_it.c **** /* USER CODE END BusFault_IRQn 0 */
118:Core/Src/stm32f1xx_it.c **** while (1)
100 .loc 1 118 3 discriminator 1 view .LVU9
119:Core/Src/stm32f1xx_it.c **** {
120:Core/Src/stm32f1xx_it.c **** /* USER CODE BEGIN W1_BusFault_IRQn 0 */
121:Core/Src/stm32f1xx_it.c **** /* USER CODE END W1_BusFault_IRQn 0 */
122:Core/Src/stm32f1xx_it.c **** }
101 .loc 1 122 3 discriminator 1 view .LVU10
102 0000 FEE7 b .L7
103 .cfi_endproc
104 .LFE68:
106 .section .text.UsageFault_Handler,"ax",%progbits
107 .align 1
108 .global UsageFault_Handler
109 .syntax unified
110 .thumb
111 .thumb_func
112 .fpu softvfp
114 UsageFault_Handler:
115 .LFB69:
ARM GAS /tmp/ccOMxQCE.s page 5
123:Core/Src/stm32f1xx_it.c **** }
124:Core/Src/stm32f1xx_it.c ****
125:Core/Src/stm32f1xx_it.c **** /**
126:Core/Src/stm32f1xx_it.c **** * @brief This function handles Undefined instruction or illegal state.
127:Core/Src/stm32f1xx_it.c **** */
128:Core/Src/stm32f1xx_it.c **** void UsageFault_Handler(void)
129:Core/Src/stm32f1xx_it.c **** {
116 .loc 1 129 1 view -0
117 .cfi_startproc
118 @ Volatile: function does not return.
119 @ args = 0, pretend = 0, frame = 0
120 @ frame_needed = 0, uses_anonymous_args = 0
121 @ link register save eliminated.
122 .L9:
130:Core/Src/stm32f1xx_it.c **** /* USER CODE BEGIN UsageFault_IRQn 0 */
131:Core/Src/stm32f1xx_it.c ****
132:Core/Src/stm32f1xx_it.c **** /* USER CODE END UsageFault_IRQn 0 */
133:Core/Src/stm32f1xx_it.c **** while (1)
123 .loc 1 133 3 discriminator 1 view .LVU12
134:Core/Src/stm32f1xx_it.c **** {
135:Core/Src/stm32f1xx_it.c **** /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
136:Core/Src/stm32f1xx_it.c **** /* USER CODE END W1_UsageFault_IRQn 0 */
137:Core/Src/stm32f1xx_it.c **** }
124 .loc 1 137 3 discriminator 1 view .LVU13
125 0000 FEE7 b .L9
126 .cfi_endproc
127 .LFE69:
129 .section .text.SVC_Handler,"ax",%progbits
130 .align 1
131 .global SVC_Handler
132 .syntax unified
133 .thumb
134 .thumb_func
135 .fpu softvfp
137 SVC_Handler:
138 .LFB70:
138:Core/Src/stm32f1xx_it.c **** }
139:Core/Src/stm32f1xx_it.c ****
140:Core/Src/stm32f1xx_it.c **** /**
141:Core/Src/stm32f1xx_it.c **** * @brief This function handles System service call via SWI instruction.
142:Core/Src/stm32f1xx_it.c **** */
143:Core/Src/stm32f1xx_it.c **** void SVC_Handler(void)
144:Core/Src/stm32f1xx_it.c **** {
139 .loc 1 144 1 view -0
140 .cfi_startproc
141 @ args = 0, pretend = 0, frame = 0
142 @ frame_needed = 0, uses_anonymous_args = 0
143 @ link register save eliminated.
145:Core/Src/stm32f1xx_it.c **** /* USER CODE BEGIN SVCall_IRQn 0 */
146:Core/Src/stm32f1xx_it.c ****
147:Core/Src/stm32f1xx_it.c **** /* USER CODE END SVCall_IRQn 0 */
148:Core/Src/stm32f1xx_it.c **** /* USER CODE BEGIN SVCall_IRQn 1 */
149:Core/Src/stm32f1xx_it.c ****
150:Core/Src/stm32f1xx_it.c **** /* USER CODE END SVCall_IRQn 1 */
151:Core/Src/stm32f1xx_it.c **** }
144 .loc 1 151 1 view .LVU15
145 0000 7047 bx lr
ARM GAS /tmp/ccOMxQCE.s page 6
146 .cfi_endproc
147 .LFE70:
149 .section .text.DebugMon_Handler,"ax",%progbits
150 .align 1
151 .global DebugMon_Handler
152 .syntax unified
153 .thumb
154 .thumb_func
155 .fpu softvfp
157 DebugMon_Handler:
158 .LFB71:
152:Core/Src/stm32f1xx_it.c ****
153:Core/Src/stm32f1xx_it.c **** /**
154:Core/Src/stm32f1xx_it.c **** * @brief This function handles Debug monitor.
155:Core/Src/stm32f1xx_it.c **** */
156:Core/Src/stm32f1xx_it.c **** void DebugMon_Handler(void)
157:Core/Src/stm32f1xx_it.c **** {
159 .loc 1 157 1 view -0
160 .cfi_startproc
161 @ args = 0, pretend = 0, frame = 0
162 @ frame_needed = 0, uses_anonymous_args = 0
163 @ link register save eliminated.
158:Core/Src/stm32f1xx_it.c **** /* USER CODE BEGIN DebugMonitor_IRQn 0 */
159:Core/Src/stm32f1xx_it.c ****
160:Core/Src/stm32f1xx_it.c **** /* USER CODE END DebugMonitor_IRQn 0 */
161:Core/Src/stm32f1xx_it.c **** /* USER CODE BEGIN DebugMonitor_IRQn 1 */
162:Core/Src/stm32f1xx_it.c ****
163:Core/Src/stm32f1xx_it.c **** /* USER CODE END DebugMonitor_IRQn 1 */
164:Core/Src/stm32f1xx_it.c **** }
164 .loc 1 164 1 view .LVU17
165 0000 7047 bx lr
166 .cfi_endproc
167 .LFE71:
169 .section .text.PendSV_Handler,"ax",%progbits
170 .align 1
171 .global PendSV_Handler
172 .syntax unified
173 .thumb
174 .thumb_func
175 .fpu softvfp
177 PendSV_Handler:
178 .LFB72:
165:Core/Src/stm32f1xx_it.c ****
166:Core/Src/stm32f1xx_it.c **** /**
167:Core/Src/stm32f1xx_it.c **** * @brief This function handles Pendable request for system service.
168:Core/Src/stm32f1xx_it.c **** */
169:Core/Src/stm32f1xx_it.c **** void PendSV_Handler(void)
170:Core/Src/stm32f1xx_it.c **** {
179 .loc 1 170 1 view -0
180 .cfi_startproc
181 @ args = 0, pretend = 0, frame = 0
182 @ frame_needed = 0, uses_anonymous_args = 0
183 @ link register save eliminated.
171:Core/Src/stm32f1xx_it.c **** /* USER CODE BEGIN PendSV_IRQn 0 */
172:Core/Src/stm32f1xx_it.c ****
173:Core/Src/stm32f1xx_it.c **** /* USER CODE END PendSV_IRQn 0 */
174:Core/Src/stm32f1xx_it.c **** /* USER CODE BEGIN PendSV_IRQn 1 */
ARM GAS /tmp/ccOMxQCE.s page 7
175:Core/Src/stm32f1xx_it.c ****
176:Core/Src/stm32f1xx_it.c **** /* USER CODE END PendSV_IRQn 1 */
177:Core/Src/stm32f1xx_it.c **** }
184 .loc 1 177 1 view .LVU19
185 0000 7047 bx lr
186 .cfi_endproc
187 .LFE72:
189 .section .text.SysTick_Handler,"ax",%progbits
190 .align 1
191 .global SysTick_Handler
192 .syntax unified
193 .thumb
194 .thumb_func
195 .fpu softvfp
197 SysTick_Handler:
198 .LFB73:
178:Core/Src/stm32f1xx_it.c ****
179:Core/Src/stm32f1xx_it.c **** /**
180:Core/Src/stm32f1xx_it.c **** * @brief This function handles System tick timer.
181:Core/Src/stm32f1xx_it.c **** */
182:Core/Src/stm32f1xx_it.c **** void SysTick_Handler(void)
183:Core/Src/stm32f1xx_it.c **** {
199 .loc 1 183 1 view -0
200 .cfi_startproc
201 @ args = 0, pretend = 0, frame = 0
202 @ frame_needed = 0, uses_anonymous_args = 0
203 0000 08B5 push {r3, lr}
204 .LCFI0:
205 .cfi_def_cfa_offset 8
206 .cfi_offset 3, -8
207 .cfi_offset 14, -4
184:Core/Src/stm32f1xx_it.c **** /* USER CODE BEGIN SysTick_IRQn 0 */
185:Core/Src/stm32f1xx_it.c ****
186:Core/Src/stm32f1xx_it.c **** /* USER CODE END SysTick_IRQn 0 */
187:Core/Src/stm32f1xx_it.c **** HAL_IncTick();
208 .loc 1 187 3 view .LVU21
209 0002 FFF7FEFF bl HAL_IncTick
210 .LVL0:
188:Core/Src/stm32f1xx_it.c **** /* USER CODE BEGIN SysTick_IRQn 1 */
189:Core/Src/stm32f1xx_it.c ****
190:Core/Src/stm32f1xx_it.c **** /* USER CODE END SysTick_IRQn 1 */
191:Core/Src/stm32f1xx_it.c **** }
211 .loc 1 191 1 is_stmt 0 view .LVU22
212 0006 08BD pop {r3, pc}
213 .cfi_endproc
214 .LFE73:
216 .text
217 .Letext0:
218 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h"
219 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h"
220 .file 4 "Drivers/CMSIS/Include/core_cm3.h"
221 .file 5 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h"
222 .file 6 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h"
ARM GAS /tmp/ccOMxQCE.s page 8
DEFINED SYMBOLS
*ABS*:0000000000000000 stm32f1xx_it.c
/tmp/ccOMxQCE.s:16 .text.NMI_Handler:0000000000000000 $t
/tmp/ccOMxQCE.s:24 .text.NMI_Handler:0000000000000000 NMI_Handler
/tmp/ccOMxQCE.s:38 .text.HardFault_Handler:0000000000000000 $t
/tmp/ccOMxQCE.s:45 .text.HardFault_Handler:0000000000000000 HardFault_Handler
/tmp/ccOMxQCE.s:61 .text.MemManage_Handler:0000000000000000 $t
/tmp/ccOMxQCE.s:68 .text.MemManage_Handler:0000000000000000 MemManage_Handler
/tmp/ccOMxQCE.s:84 .text.BusFault_Handler:0000000000000000 $t
/tmp/ccOMxQCE.s:91 .text.BusFault_Handler:0000000000000000 BusFault_Handler
/tmp/ccOMxQCE.s:107 .text.UsageFault_Handler:0000000000000000 $t
/tmp/ccOMxQCE.s:114 .text.UsageFault_Handler:0000000000000000 UsageFault_Handler
/tmp/ccOMxQCE.s:130 .text.SVC_Handler:0000000000000000 $t
/tmp/ccOMxQCE.s:137 .text.SVC_Handler:0000000000000000 SVC_Handler
/tmp/ccOMxQCE.s:150 .text.DebugMon_Handler:0000000000000000 $t
/tmp/ccOMxQCE.s:157 .text.DebugMon_Handler:0000000000000000 DebugMon_Handler
/tmp/ccOMxQCE.s:170 .text.PendSV_Handler:0000000000000000 $t
/tmp/ccOMxQCE.s:177 .text.PendSV_Handler:0000000000000000 PendSV_Handler
/tmp/ccOMxQCE.s:190 .text.SysTick_Handler:0000000000000000 $t
/tmp/ccOMxQCE.s:197 .text.SysTick_Handler:0000000000000000 SysTick_Handler
UNDEFINED SYMBOLS
HAL_IncTick

BIN
rusci-firmware/build/stm32f1xx_it.o Normal file
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68
rusci-firmware/build/system_stm32f1xx.d Normal file
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build/system_stm32f1xx.o: Core/Src/system_stm32f1xx.c \
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h \
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h \
Drivers/CMSIS/Include/core_cm3.h Drivers/CMSIS/Include/cmsis_version.h \
Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h \
Core/Inc/stm32f1xx_hal_conf.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h \
Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h:
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h:
Drivers/CMSIS/Include/core_cm3.h:
Drivers/CMSIS/Include/cmsis_version.h:
Drivers/CMSIS/Include/cmsis_compiler.h:
Drivers/CMSIS/Include/cmsis_gcc.h:
Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h:
Core/Inc/stm32f1xx_hal_conf.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h:
Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h:
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h:

648
rusci-firmware/build/system_stm32f1xx.lst Normal file
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ARM GAS /tmp/ccHSpkP2.s page 1
1 .cpu cortex-m3
2 .eabi_attribute 20, 1
3 .eabi_attribute 21, 1
4 .eabi_attribute 23, 3
5 .eabi_attribute 24, 1
6 .eabi_attribute 25, 1
7 .eabi_attribute 26, 1
8 .eabi_attribute 30, 1
9 .eabi_attribute 34, 1
10 .eabi_attribute 18, 4
11 .file "system_stm32f1xx.c"
12 .text
13 .Ltext0:
14 .cfi_sections .debug_frame
15 .section .text.SystemInit,"ax",%progbits
16 .align 1
17 .global SystemInit
18 .arch armv7-m
19 .syntax unified
20 .thumb
21 .thumb_func
22 .fpu softvfp
24 SystemInit:
25 .LFB65:
26 .file 1 "Core/Src/system_stm32f1xx.c"
1:Core/Src/system_stm32f1xx.c **** /**
2:Core/Src/system_stm32f1xx.c **** ******************************************************************************
3:Core/Src/system_stm32f1xx.c **** * @file system_stm32f1xx.c
4:Core/Src/system_stm32f1xx.c **** * @author MCD Application Team
5:Core/Src/system_stm32f1xx.c **** * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
6:Core/Src/system_stm32f1xx.c **** *
7:Core/Src/system_stm32f1xx.c **** * 1. This file provides two functions and one global variable to be called from
8:Core/Src/system_stm32f1xx.c **** * user application:
9:Core/Src/system_stm32f1xx.c **** * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
10:Core/Src/system_stm32f1xx.c **** * factors, AHB/APBx prescalers and Flash settings).
11:Core/Src/system_stm32f1xx.c **** * This function is called at startup just after reset and
12:Core/Src/system_stm32f1xx.c **** * before branch to main program. This call is made inside
13:Core/Src/system_stm32f1xx.c **** * the "startup_stm32f1xx_xx.s" file.
14:Core/Src/system_stm32f1xx.c **** *
15:Core/Src/system_stm32f1xx.c **** * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
16:Core/Src/system_stm32f1xx.c **** * by the user application to setup the SysTick
17:Core/Src/system_stm32f1xx.c **** * timer or configure other parameters.
18:Core/Src/system_stm32f1xx.c **** *
19:Core/Src/system_stm32f1xx.c **** * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
20:Core/Src/system_stm32f1xx.c **** * be called whenever the core clock is changed
21:Core/Src/system_stm32f1xx.c **** * during program execution.
22:Core/Src/system_stm32f1xx.c **** *
23:Core/Src/system_stm32f1xx.c **** * 2. After each device reset the HSI (8 MHz) is used as system clock source.
24:Core/Src/system_stm32f1xx.c **** * Then SystemInit() function is called, in "startup_stm32f1xx_xx.s" file, to
25:Core/Src/system_stm32f1xx.c **** * configure the system clock before to branch to main program.
26:Core/Src/system_stm32f1xx.c **** *
27:Core/Src/system_stm32f1xx.c **** * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on
28:Core/Src/system_stm32f1xx.c **** * the product used), refer to "HSE_VALUE".
29:Core/Src/system_stm32f1xx.c **** * When HSE is used as system clock source, directly or through PLL, and you
30:Core/Src/system_stm32f1xx.c **** * are using different crystal you have to adapt the HSE value to your own
31:Core/Src/system_stm32f1xx.c **** * configuration.
32:Core/Src/system_stm32f1xx.c **** *
ARM GAS /tmp/ccHSpkP2.s page 2
33:Core/Src/system_stm32f1xx.c **** ******************************************************************************
34:Core/Src/system_stm32f1xx.c **** * @attention
35:Core/Src/system_stm32f1xx.c **** *
36:Core/Src/system_stm32f1xx.c **** * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
37:Core/Src/system_stm32f1xx.c **** * All rights reserved.</center></h2>
38:Core/Src/system_stm32f1xx.c **** *
39:Core/Src/system_stm32f1xx.c **** * This software component is licensed by ST under BSD 3-Clause license,
40:Core/Src/system_stm32f1xx.c **** * the "License"; You may not use this file except in compliance with the
41:Core/Src/system_stm32f1xx.c **** * License. You may obtain a copy of the License at:
42:Core/Src/system_stm32f1xx.c **** * opensource.org/licenses/BSD-3-Clause
43:Core/Src/system_stm32f1xx.c **** *
44:Core/Src/system_stm32f1xx.c **** ******************************************************************************
45:Core/Src/system_stm32f1xx.c **** */
46:Core/Src/system_stm32f1xx.c ****
47:Core/Src/system_stm32f1xx.c **** /** @addtogroup CMSIS
48:Core/Src/system_stm32f1xx.c **** * @{
49:Core/Src/system_stm32f1xx.c **** */
50:Core/Src/system_stm32f1xx.c ****
51:Core/Src/system_stm32f1xx.c **** /** @addtogroup stm32f1xx_system
52:Core/Src/system_stm32f1xx.c **** * @{
53:Core/Src/system_stm32f1xx.c **** */
54:Core/Src/system_stm32f1xx.c ****
55:Core/Src/system_stm32f1xx.c **** /** @addtogroup STM32F1xx_System_Private_Includes
56:Core/Src/system_stm32f1xx.c **** * @{
57:Core/Src/system_stm32f1xx.c **** */
58:Core/Src/system_stm32f1xx.c ****
59:Core/Src/system_stm32f1xx.c **** #include "stm32f1xx.h"
60:Core/Src/system_stm32f1xx.c ****
61:Core/Src/system_stm32f1xx.c **** /**
62:Core/Src/system_stm32f1xx.c **** * @}
63:Core/Src/system_stm32f1xx.c **** */
64:Core/Src/system_stm32f1xx.c ****
65:Core/Src/system_stm32f1xx.c **** /** @addtogroup STM32F1xx_System_Private_TypesDefinitions
66:Core/Src/system_stm32f1xx.c **** * @{
67:Core/Src/system_stm32f1xx.c **** */
68:Core/Src/system_stm32f1xx.c ****
69:Core/Src/system_stm32f1xx.c **** /**
70:Core/Src/system_stm32f1xx.c **** * @}
71:Core/Src/system_stm32f1xx.c **** */
72:Core/Src/system_stm32f1xx.c ****
73:Core/Src/system_stm32f1xx.c **** /** @addtogroup STM32F1xx_System_Private_Defines
74:Core/Src/system_stm32f1xx.c **** * @{
75:Core/Src/system_stm32f1xx.c **** */
76:Core/Src/system_stm32f1xx.c ****
77:Core/Src/system_stm32f1xx.c **** #if !defined (HSE_VALUE)
78:Core/Src/system_stm32f1xx.c **** #define HSE_VALUE 8000000U /*!< Default value of the External oscillator in Hz.
79:Core/Src/system_stm32f1xx.c **** This value can be provided and adapted by the user
80:Core/Src/system_stm32f1xx.c **** #endif /* HSE_VALUE */
81:Core/Src/system_stm32f1xx.c ****
82:Core/Src/system_stm32f1xx.c **** #if !defined (HSI_VALUE)
83:Core/Src/system_stm32f1xx.c **** #define HSI_VALUE 8000000U /*!< Default value of the Internal oscillator in Hz.
84:Core/Src/system_stm32f1xx.c **** This value can be provided and adapted by the user
85:Core/Src/system_stm32f1xx.c **** #endif /* HSI_VALUE */
86:Core/Src/system_stm32f1xx.c ****
87:Core/Src/system_stm32f1xx.c **** /*!< Uncomment the following line if you need to use external SRAM */
88:Core/Src/system_stm32f1xx.c **** #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) ||
89:Core/Src/system_stm32f1xx.c **** /* #define DATA_IN_ExtSRAM */
ARM GAS /tmp/ccHSpkP2.s page 3
90:Core/Src/system_stm32f1xx.c **** #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
91:Core/Src/system_stm32f1xx.c ****
92:Core/Src/system_stm32f1xx.c **** /* Note: Following vector table addresses must be defined in line with linker
93:Core/Src/system_stm32f1xx.c **** configuration. */
94:Core/Src/system_stm32f1xx.c **** /*!< Uncomment the following line if you need to relocate the vector table
95:Core/Src/system_stm32f1xx.c **** anywhere in Flash or Sram, else the vector table is kept at the automatic
96:Core/Src/system_stm32f1xx.c **** remap of boot address selected */
97:Core/Src/system_stm32f1xx.c **** /* #define USER_VECT_TAB_ADDRESS */
98:Core/Src/system_stm32f1xx.c ****
99:Core/Src/system_stm32f1xx.c **** #if defined(USER_VECT_TAB_ADDRESS)
100:Core/Src/system_stm32f1xx.c **** /*!< Uncomment the following line if you need to relocate your vector Table
101:Core/Src/system_stm32f1xx.c **** in Sram else user remap will be done in Flash. */
102:Core/Src/system_stm32f1xx.c **** /* #define VECT_TAB_SRAM */
103:Core/Src/system_stm32f1xx.c **** #if defined(VECT_TAB_SRAM)
104:Core/Src/system_stm32f1xx.c **** #define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field.
105:Core/Src/system_stm32f1xx.c **** This value must be a multiple of 0x200. */
106:Core/Src/system_stm32f1xx.c **** #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
107:Core/Src/system_stm32f1xx.c **** This value must be a multiple of 0x200. */
108:Core/Src/system_stm32f1xx.c **** #else
109:Core/Src/system_stm32f1xx.c **** #define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
110:Core/Src/system_stm32f1xx.c **** This value must be a multiple of 0x200. */
111:Core/Src/system_stm32f1xx.c **** #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
112:Core/Src/system_stm32f1xx.c **** This value must be a multiple of 0x200. */
113:Core/Src/system_stm32f1xx.c **** #endif /* VECT_TAB_SRAM */
114:Core/Src/system_stm32f1xx.c **** #endif /* USER_VECT_TAB_ADDRESS */
115:Core/Src/system_stm32f1xx.c ****
116:Core/Src/system_stm32f1xx.c **** /******************************************************************************/
117:Core/Src/system_stm32f1xx.c ****
118:Core/Src/system_stm32f1xx.c **** /**
119:Core/Src/system_stm32f1xx.c **** * @}
120:Core/Src/system_stm32f1xx.c **** */
121:Core/Src/system_stm32f1xx.c ****
122:Core/Src/system_stm32f1xx.c **** /** @addtogroup STM32F1xx_System_Private_Macros
123:Core/Src/system_stm32f1xx.c **** * @{
124:Core/Src/system_stm32f1xx.c **** */
125:Core/Src/system_stm32f1xx.c ****
126:Core/Src/system_stm32f1xx.c **** /**
127:Core/Src/system_stm32f1xx.c **** * @}
128:Core/Src/system_stm32f1xx.c **** */
129:Core/Src/system_stm32f1xx.c ****
130:Core/Src/system_stm32f1xx.c **** /** @addtogroup STM32F1xx_System_Private_Variables
131:Core/Src/system_stm32f1xx.c **** * @{
132:Core/Src/system_stm32f1xx.c **** */
133:Core/Src/system_stm32f1xx.c ****
134:Core/Src/system_stm32f1xx.c **** /* This variable is updated in three ways:
135:Core/Src/system_stm32f1xx.c **** 1) by calling CMSIS function SystemCoreClockUpdate()
136:Core/Src/system_stm32f1xx.c **** 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
137:Core/Src/system_stm32f1xx.c **** 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
138:Core/Src/system_stm32f1xx.c **** Note: If you use this function to configure the system clock; then there
139:Core/Src/system_stm32f1xx.c **** is no need to call the 2 first functions listed above, since SystemCoreClock
140:Core/Src/system_stm32f1xx.c **** variable is updated automatically.
141:Core/Src/system_stm32f1xx.c **** */
142:Core/Src/system_stm32f1xx.c **** uint32_t SystemCoreClock = 16000000;
143:Core/Src/system_stm32f1xx.c **** const uint8_t AHBPrescTable[16U] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
144:Core/Src/system_stm32f1xx.c **** const uint8_t APBPrescTable[8U] = {0, 0, 0, 0, 1, 2, 3, 4};
145:Core/Src/system_stm32f1xx.c ****
146:Core/Src/system_stm32f1xx.c **** /**
ARM GAS /tmp/ccHSpkP2.s page 4
147:Core/Src/system_stm32f1xx.c **** * @}
148:Core/Src/system_stm32f1xx.c **** */
149:Core/Src/system_stm32f1xx.c ****
150:Core/Src/system_stm32f1xx.c **** /** @addtogroup STM32F1xx_System_Private_FunctionPrototypes
151:Core/Src/system_stm32f1xx.c **** * @{
152:Core/Src/system_stm32f1xx.c **** */
153:Core/Src/system_stm32f1xx.c ****
154:Core/Src/system_stm32f1xx.c **** #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) ||
155:Core/Src/system_stm32f1xx.c **** #ifdef DATA_IN_ExtSRAM
156:Core/Src/system_stm32f1xx.c **** static void SystemInit_ExtMemCtl(void);
157:Core/Src/system_stm32f1xx.c **** #endif /* DATA_IN_ExtSRAM */
158:Core/Src/system_stm32f1xx.c **** #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
159:Core/Src/system_stm32f1xx.c ****
160:Core/Src/system_stm32f1xx.c **** /**
161:Core/Src/system_stm32f1xx.c **** * @}
162:Core/Src/system_stm32f1xx.c **** */
163:Core/Src/system_stm32f1xx.c ****
164:Core/Src/system_stm32f1xx.c **** /** @addtogroup STM32F1xx_System_Private_Functions
165:Core/Src/system_stm32f1xx.c **** * @{
166:Core/Src/system_stm32f1xx.c **** */
167:Core/Src/system_stm32f1xx.c ****
168:Core/Src/system_stm32f1xx.c **** /**
169:Core/Src/system_stm32f1xx.c **** * @brief Setup the microcontroller system
170:Core/Src/system_stm32f1xx.c **** * Initialize the Embedded Flash Interface, the PLL and update the
171:Core/Src/system_stm32f1xx.c **** * SystemCoreClock variable.
172:Core/Src/system_stm32f1xx.c **** * @note This function should be used only after reset.
173:Core/Src/system_stm32f1xx.c **** * @param None
174:Core/Src/system_stm32f1xx.c **** * @retval None
175:Core/Src/system_stm32f1xx.c **** */
176:Core/Src/system_stm32f1xx.c **** void SystemInit (void)
177:Core/Src/system_stm32f1xx.c **** {
27 .loc 1 177 1 view -0
28 .cfi_startproc
29 @ args = 0, pretend = 0, frame = 0
30 @ frame_needed = 0, uses_anonymous_args = 0
31 @ link register save eliminated.
178:Core/Src/system_stm32f1xx.c **** #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) ||
179:Core/Src/system_stm32f1xx.c **** #ifdef DATA_IN_ExtSRAM
180:Core/Src/system_stm32f1xx.c **** SystemInit_ExtMemCtl();
181:Core/Src/system_stm32f1xx.c **** #endif /* DATA_IN_ExtSRAM */
182:Core/Src/system_stm32f1xx.c **** #endif
183:Core/Src/system_stm32f1xx.c ****
184:Core/Src/system_stm32f1xx.c **** /* Configure the Vector Table location -------------------------------------*/
185:Core/Src/system_stm32f1xx.c **** #if defined(USER_VECT_TAB_ADDRESS)
186:Core/Src/system_stm32f1xx.c **** SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM.
187:Core/Src/system_stm32f1xx.c **** #endif /* USER_VECT_TAB_ADDRESS */
188:Core/Src/system_stm32f1xx.c **** }
32 .loc 1 188 1 view .LVU1
33 0000 7047 bx lr
34 .cfi_endproc
35 .LFE65:
37 .section .text.SystemCoreClockUpdate,"ax",%progbits
38 .align 1
39 .global SystemCoreClockUpdate
40 .syntax unified
41 .thumb
42 .thumb_func
ARM GAS /tmp/ccHSpkP2.s page 5
43 .fpu softvfp
45 SystemCoreClockUpdate:
46 .LFB66:
189:Core/Src/system_stm32f1xx.c ****
190:Core/Src/system_stm32f1xx.c **** /**
191:Core/Src/system_stm32f1xx.c **** * @brief Update SystemCoreClock variable according to Clock Register Values.
192:Core/Src/system_stm32f1xx.c **** * The SystemCoreClock variable contains the core clock (HCLK), it can
193:Core/Src/system_stm32f1xx.c **** * be used by the user application to setup the SysTick timer or configure
194:Core/Src/system_stm32f1xx.c **** * other parameters.
195:Core/Src/system_stm32f1xx.c **** *
196:Core/Src/system_stm32f1xx.c **** * @note Each time the core clock (HCLK) changes, this function must be called
197:Core/Src/system_stm32f1xx.c **** * to update SystemCoreClock variable value. Otherwise, any configuration
198:Core/Src/system_stm32f1xx.c **** * based on this variable will be incorrect.
199:Core/Src/system_stm32f1xx.c **** *
200:Core/Src/system_stm32f1xx.c **** * @note - The system frequency computed by this function is not the real
201:Core/Src/system_stm32f1xx.c **** * frequency in the chip. It is calculated based on the predefined
202:Core/Src/system_stm32f1xx.c **** * constant and the selected clock source:
203:Core/Src/system_stm32f1xx.c **** *
204:Core/Src/system_stm32f1xx.c **** * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
205:Core/Src/system_stm32f1xx.c **** *
206:Core/Src/system_stm32f1xx.c **** * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
207:Core/Src/system_stm32f1xx.c **** *
208:Core/Src/system_stm32f1xx.c **** * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
209:Core/Src/system_stm32f1xx.c **** * or HSI_VALUE(*) multiplied by the PLL factors.
210:Core/Src/system_stm32f1xx.c **** *
211:Core/Src/system_stm32f1xx.c **** * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
212:Core/Src/system_stm32f1xx.c **** * 8 MHz) but the real value may vary depending on the variations
213:Core/Src/system_stm32f1xx.c **** * in voltage and temperature.
214:Core/Src/system_stm32f1xx.c **** *
215:Core/Src/system_stm32f1xx.c **** * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
216:Core/Src/system_stm32f1xx.c **** * 8 MHz or 25 MHz, depending on the product used), user has to ensure
217:Core/Src/system_stm32f1xx.c **** * that HSE_VALUE is same as the real frequency of the crystal used.
218:Core/Src/system_stm32f1xx.c **** * Otherwise, this function may have wrong result.
219:Core/Src/system_stm32f1xx.c **** *
220:Core/Src/system_stm32f1xx.c **** * - The result of this function could be not correct when using fractional
221:Core/Src/system_stm32f1xx.c **** * value for HSE crystal.
222:Core/Src/system_stm32f1xx.c **** * @param None
223:Core/Src/system_stm32f1xx.c **** * @retval None
224:Core/Src/system_stm32f1xx.c **** */
225:Core/Src/system_stm32f1xx.c **** void SystemCoreClockUpdate (void)
226:Core/Src/system_stm32f1xx.c **** {
47 .loc 1 226 1 view -0
48 .cfi_startproc
49 @ args = 0, pretend = 0, frame = 0
50 @ frame_needed = 0, uses_anonymous_args = 0
51 @ link register save eliminated.
227:Core/Src/system_stm32f1xx.c **** uint32_t tmp = 0U, pllmull = 0U, pllsource = 0U;
52 .loc 1 227 3 view .LVU3
53 .LVL0:
228:Core/Src/system_stm32f1xx.c ****
229:Core/Src/system_stm32f1xx.c **** #if defined(STM32F105xC) || defined(STM32F107xC)
230:Core/Src/system_stm32f1xx.c **** uint32_t prediv1source = 0U, prediv1factor = 0U, prediv2factor = 0U, pll2mull = 0U;
231:Core/Src/system_stm32f1xx.c **** #endif /* STM32F105xC */
232:Core/Src/system_stm32f1xx.c ****
233:Core/Src/system_stm32f1xx.c **** #if defined(STM32F100xB) || defined(STM32F100xE)
234:Core/Src/system_stm32f1xx.c **** uint32_t prediv1factor = 0U;
235:Core/Src/system_stm32f1xx.c **** #endif /* STM32F100xB or STM32F100xE */
ARM GAS /tmp/ccHSpkP2.s page 6
236:Core/Src/system_stm32f1xx.c ****
237:Core/Src/system_stm32f1xx.c **** /* Get SYSCLK source -------------------------------------------------------*/
238:Core/Src/system_stm32f1xx.c **** tmp = RCC->CFGR & RCC_CFGR_SWS;
54 .loc 1 238 3 view .LVU4
55 .loc 1 238 12 is_stmt 0 view .LVU5
56 0000 1F4B ldr r3, .L10
57 0002 5B68 ldr r3, [r3, #4]
58 .loc 1 238 7 view .LVU6
59 0004 03F00C03 and r3, r3, #12
60 .LVL1:
239:Core/Src/system_stm32f1xx.c ****
240:Core/Src/system_stm32f1xx.c **** switch (tmp)
61 .loc 1 240 3 is_stmt 1 view .LVU7
62 0008 042B cmp r3, #4
63 000a 14D0 beq .L3
64 000c 082B cmp r3, #8
65 000e 16D0 beq .L4
66 0010 1BB1 cbz r3, .L9
241:Core/Src/system_stm32f1xx.c **** {
242:Core/Src/system_stm32f1xx.c **** case 0x00U: /* HSI used as system clock */
243:Core/Src/system_stm32f1xx.c **** SystemCoreClock = HSI_VALUE;
244:Core/Src/system_stm32f1xx.c **** break;
245:Core/Src/system_stm32f1xx.c **** case 0x04U: /* HSE used as system clock */
246:Core/Src/system_stm32f1xx.c **** SystemCoreClock = HSE_VALUE;
247:Core/Src/system_stm32f1xx.c **** break;
248:Core/Src/system_stm32f1xx.c **** case 0x08U: /* PLL used as system clock */
249:Core/Src/system_stm32f1xx.c ****
250:Core/Src/system_stm32f1xx.c **** /* Get PLL clock source and multiplication factor ----------------------*/
251:Core/Src/system_stm32f1xx.c **** pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
252:Core/Src/system_stm32f1xx.c **** pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
253:Core/Src/system_stm32f1xx.c ****
254:Core/Src/system_stm32f1xx.c **** #if !defined(STM32F105xC) && !defined(STM32F107xC)
255:Core/Src/system_stm32f1xx.c **** pllmull = ( pllmull >> 18U) + 2U;
256:Core/Src/system_stm32f1xx.c ****
257:Core/Src/system_stm32f1xx.c **** if (pllsource == 0x00U)
258:Core/Src/system_stm32f1xx.c **** {
259:Core/Src/system_stm32f1xx.c **** /* HSI oscillator clock divided by 2 selected as PLL clock entry */
260:Core/Src/system_stm32f1xx.c **** SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;
261:Core/Src/system_stm32f1xx.c **** }
262:Core/Src/system_stm32f1xx.c **** else
263:Core/Src/system_stm32f1xx.c **** {
264:Core/Src/system_stm32f1xx.c **** #if defined(STM32F100xB) || defined(STM32F100xE)
265:Core/Src/system_stm32f1xx.c **** prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;
266:Core/Src/system_stm32f1xx.c **** /* HSE oscillator clock selected as PREDIV1 clock entry */
267:Core/Src/system_stm32f1xx.c **** SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
268:Core/Src/system_stm32f1xx.c **** #else
269:Core/Src/system_stm32f1xx.c **** /* HSE selected as PLL clock entry */
270:Core/Src/system_stm32f1xx.c **** if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
271:Core/Src/system_stm32f1xx.c **** {/* HSE oscillator clock divided by 2 */
272:Core/Src/system_stm32f1xx.c **** SystemCoreClock = (HSE_VALUE >> 1U) * pllmull;
273:Core/Src/system_stm32f1xx.c **** }
274:Core/Src/system_stm32f1xx.c **** else
275:Core/Src/system_stm32f1xx.c **** {
276:Core/Src/system_stm32f1xx.c **** SystemCoreClock = HSE_VALUE * pllmull;
277:Core/Src/system_stm32f1xx.c **** }
278:Core/Src/system_stm32f1xx.c **** #endif
279:Core/Src/system_stm32f1xx.c **** }
ARM GAS /tmp/ccHSpkP2.s page 7
280:Core/Src/system_stm32f1xx.c **** #else
281:Core/Src/system_stm32f1xx.c **** pllmull = pllmull >> 18U;
282:Core/Src/system_stm32f1xx.c ****
283:Core/Src/system_stm32f1xx.c **** if (pllmull != 0x0DU)
284:Core/Src/system_stm32f1xx.c **** {
285:Core/Src/system_stm32f1xx.c **** pllmull += 2U;
286:Core/Src/system_stm32f1xx.c **** }
287:Core/Src/system_stm32f1xx.c **** else
288:Core/Src/system_stm32f1xx.c **** { /* PLL multiplication factor = PLL input clock * 6.5 */
289:Core/Src/system_stm32f1xx.c **** pllmull = 13U / 2U;
290:Core/Src/system_stm32f1xx.c **** }
291:Core/Src/system_stm32f1xx.c ****
292:Core/Src/system_stm32f1xx.c **** if (pllsource == 0x00U)
293:Core/Src/system_stm32f1xx.c **** {
294:Core/Src/system_stm32f1xx.c **** /* HSI oscillator clock divided by 2 selected as PLL clock entry */
295:Core/Src/system_stm32f1xx.c **** SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;
296:Core/Src/system_stm32f1xx.c **** }
297:Core/Src/system_stm32f1xx.c **** else
298:Core/Src/system_stm32f1xx.c **** {/* PREDIV1 selected as PLL clock entry */
299:Core/Src/system_stm32f1xx.c ****
300:Core/Src/system_stm32f1xx.c **** /* Get PREDIV1 clock source and division factor */
301:Core/Src/system_stm32f1xx.c **** prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
302:Core/Src/system_stm32f1xx.c **** prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;
303:Core/Src/system_stm32f1xx.c ****
304:Core/Src/system_stm32f1xx.c **** if (prediv1source == 0U)
305:Core/Src/system_stm32f1xx.c **** {
306:Core/Src/system_stm32f1xx.c **** /* HSE oscillator clock selected as PREDIV1 clock entry */
307:Core/Src/system_stm32f1xx.c **** SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
308:Core/Src/system_stm32f1xx.c **** }
309:Core/Src/system_stm32f1xx.c **** else
310:Core/Src/system_stm32f1xx.c **** {/* PLL2 clock selected as PREDIV1 clock entry */
311:Core/Src/system_stm32f1xx.c ****
312:Core/Src/system_stm32f1xx.c **** /* Get PREDIV2 division factor and PLL2 multiplication factor */
313:Core/Src/system_stm32f1xx.c **** prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4U) + 1U;
314:Core/Src/system_stm32f1xx.c **** pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8U) + 2U;
315:Core/Src/system_stm32f1xx.c **** SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
316:Core/Src/system_stm32f1xx.c **** }
317:Core/Src/system_stm32f1xx.c **** }
318:Core/Src/system_stm32f1xx.c **** #endif /* STM32F105xC */
319:Core/Src/system_stm32f1xx.c **** break;
320:Core/Src/system_stm32f1xx.c ****
321:Core/Src/system_stm32f1xx.c **** default:
322:Core/Src/system_stm32f1xx.c **** SystemCoreClock = HSI_VALUE;
67 .loc 1 322 7 view .LVU8
68 .loc 1 322 23 is_stmt 0 view .LVU9
69 0012 1C4B ldr r3, .L10+4
70 .LVL2:
71 .loc 1 322 23 view .LVU10
72 0014 1C4A ldr r2, .L10+8
73 0016 1A60 str r2, [r3]
323:Core/Src/system_stm32f1xx.c **** break;
74 .loc 1 323 7 is_stmt 1 view .LVU11
75 0018 02E0 b .L6
76 .LVL3:
77 .L9:
243:Core/Src/system_stm32f1xx.c **** break;
78 .loc 1 243 7 view .LVU12
ARM GAS /tmp/ccHSpkP2.s page 8
243:Core/Src/system_stm32f1xx.c **** break;
79 .loc 1 243 23 is_stmt 0 view .LVU13
80 001a 1A4B ldr r3, .L10+4
81 .LVL4:
243:Core/Src/system_stm32f1xx.c **** break;
82 .loc 1 243 23 view .LVU14
83 001c 1A4A ldr r2, .L10+8
84 001e 1A60 str r2, [r3]
244:Core/Src/system_stm32f1xx.c **** case 0x04U: /* HSE used as system clock */
85 .loc 1 244 7 is_stmt 1 view .LVU15
86 .LVL5:
87 .L6:
324:Core/Src/system_stm32f1xx.c **** }
325:Core/Src/system_stm32f1xx.c ****
326:Core/Src/system_stm32f1xx.c **** /* Compute HCLK clock frequency ----------------*/
327:Core/Src/system_stm32f1xx.c **** /* Get HCLK prescaler */
328:Core/Src/system_stm32f1xx.c **** tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
88 .loc 1 328 3 view .LVU16
89 .loc 1 328 28 is_stmt 0 view .LVU17
90 0020 174B ldr r3, .L10
91 0022 5B68 ldr r3, [r3, #4]
92 .loc 1 328 52 view .LVU18
93 0024 C3F30313 ubfx r3, r3, #4, #4
94 .loc 1 328 22 view .LVU19
95 0028 184A ldr r2, .L10+12
96 002a D15C ldrb r1, [r2, r3] @ zero_extendqisi2
97 .LVL6:
329:Core/Src/system_stm32f1xx.c **** /* HCLK clock frequency */
330:Core/Src/system_stm32f1xx.c **** SystemCoreClock >>= tmp;
98 .loc 1 330 3 is_stmt 1 view .LVU20
99 .loc 1 330 19 is_stmt 0 view .LVU21
100 002c 154A ldr r2, .L10+4
101 002e 1368 ldr r3, [r2]
102 0030 CB40 lsrs r3, r3, r1
103 0032 1360 str r3, [r2]
331:Core/Src/system_stm32f1xx.c **** }
104 .loc 1 331 1 view .LVU22
105 0034 7047 bx lr
106 .LVL7:
107 .L3:
246:Core/Src/system_stm32f1xx.c **** break;
108 .loc 1 246 7 is_stmt 1 view .LVU23
246:Core/Src/system_stm32f1xx.c **** break;
109 .loc 1 246 23 is_stmt 0 view .LVU24
110 0036 134B ldr r3, .L10+4
111 .LVL8:
246:Core/Src/system_stm32f1xx.c **** break;
112 .loc 1 246 23 view .LVU25
113 0038 134A ldr r2, .L10+8
114 003a 1A60 str r2, [r3]
247:Core/Src/system_stm32f1xx.c **** case 0x08U: /* PLL used as system clock */
115 .loc 1 247 7 is_stmt 1 view .LVU26
116 003c F0E7 b .L6
117 .LVL9:
118 .L4:
251:Core/Src/system_stm32f1xx.c **** pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
119 .loc 1 251 7 view .LVU27
ARM GAS /tmp/ccHSpkP2.s page 9
251:Core/Src/system_stm32f1xx.c **** pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
120 .loc 1 251 20 is_stmt 0 view .LVU28
121 003e 104A ldr r2, .L10
122 0040 5368 ldr r3, [r2, #4]
123 .LVL10:
252:Core/Src/system_stm32f1xx.c ****
124 .loc 1 252 7 is_stmt 1 view .LVU29
252:Core/Src/system_stm32f1xx.c ****
125 .loc 1 252 22 is_stmt 0 view .LVU30
126 0042 5268 ldr r2, [r2, #4]
127 .LVL11:
255:Core/Src/system_stm32f1xx.c ****
128 .loc 1 255 7 is_stmt 1 view .LVU31
255:Core/Src/system_stm32f1xx.c ****
129 .loc 1 255 27 is_stmt 0 view .LVU32
130 0044 C3F38343 ubfx r3, r3, #18, #4
131 .LVL12:
255:Core/Src/system_stm32f1xx.c ****
132 .loc 1 255 15 view .LVU33
133 0048 0233 adds r3, r3, #2
134 .LVL13:
257:Core/Src/system_stm32f1xx.c **** {
135 .loc 1 257 7 is_stmt 1 view .LVU34
257:Core/Src/system_stm32f1xx.c **** {
136 .loc 1 257 10 is_stmt 0 view .LVU35
137 004a 12F4803F tst r2, #65536
138 004e 05D1 bne .L7
260:Core/Src/system_stm32f1xx.c **** }
139 .loc 1 260 9 is_stmt 1 view .LVU36
260:Core/Src/system_stm32f1xx.c **** }
140 .loc 1 260 45 is_stmt 0 view .LVU37
141 0050 0F4A ldr r2, .L10+16
142 .LVL14:
260:Core/Src/system_stm32f1xx.c **** }
143 .loc 1 260 45 view .LVU38
144 0052 02FB03F3 mul r3, r2, r3
145 .LVL15:
260:Core/Src/system_stm32f1xx.c **** }
146 .loc 1 260 25 view .LVU39
147 0056 0B4A ldr r2, .L10+4
148 0058 1360 str r3, [r2]
149 005a E1E7 b .L6
150 .LVL16:
151 .L7:
270:Core/Src/system_stm32f1xx.c **** {/* HSE oscillator clock divided by 2 */
152 .loc 1 270 9 is_stmt 1 view .LVU40
270:Core/Src/system_stm32f1xx.c **** {/* HSE oscillator clock divided by 2 */
153 .loc 1 270 17 is_stmt 0 view .LVU41
154 005c 084A ldr r2, .L10
155 .LVL17:
270:Core/Src/system_stm32f1xx.c **** {/* HSE oscillator clock divided by 2 */
156 .loc 1 270 17 view .LVU42
157 005e 5268 ldr r2, [r2, #4]
270:Core/Src/system_stm32f1xx.c **** {/* HSE oscillator clock divided by 2 */
158 .loc 1 270 12 view .LVU43
159 0060 12F4003F tst r2, #131072
160 0064 05D0 beq .L8
ARM GAS /tmp/ccHSpkP2.s page 10
272:Core/Src/system_stm32f1xx.c **** }
161 .loc 1 272 11 is_stmt 1 view .LVU44
272:Core/Src/system_stm32f1xx.c **** }
162 .loc 1 272 47 is_stmt 0 view .LVU45
163 0066 0A4A ldr r2, .L10+16
164 0068 02FB03F3 mul r3, r2, r3
165 .LVL18:
272:Core/Src/system_stm32f1xx.c **** }
166 .loc 1 272 27 view .LVU46
167 006c 054A ldr r2, .L10+4
168 006e 1360 str r3, [r2]
169 0070 D6E7 b .L6
170 .LVL19:
171 .L8:
276:Core/Src/system_stm32f1xx.c **** }
172 .loc 1 276 11 is_stmt 1 view .LVU47
276:Core/Src/system_stm32f1xx.c **** }
173 .loc 1 276 39 is_stmt 0 view .LVU48
174 0072 054A ldr r2, .L10+8
175 0074 02FB03F3 mul r3, r2, r3
176 .LVL20:
276:Core/Src/system_stm32f1xx.c **** }
177 .loc 1 276 27 view .LVU49
178 0078 024A ldr r2, .L10+4
179 007a 1360 str r3, [r2]
180 007c D0E7 b .L6
181 .L11:
182 007e 00BF .align 2
183 .L10:
184 0080 00100240 .word 1073876992
185 0084 00000000 .word .LANCHOR0
186 0088 00127A00 .word 8000000
187 008c 00000000 .word .LANCHOR1
188 0090 00093D00 .word 4000000
189 .cfi_endproc
190 .LFE66:
192 .global APBPrescTable
193 .global AHBPrescTable
194 .global SystemCoreClock
195 .section .data.SystemCoreClock,"aw"
196 .align 2
197 .set .LANCHOR0,. + 0
200 SystemCoreClock:
201 0000 0024F400 .word 16000000
202 .section .rodata.AHBPrescTable,"a"
203 .align 2
204 .set .LANCHOR1,. + 0
207 AHBPrescTable:
208 0000 00 .byte 0
209 0001 00 .byte 0
210 0002 00 .byte 0
211 0003 00 .byte 0
212 0004 00 .byte 0
213 0005 00 .byte 0
214 0006 00 .byte 0
215 0007 00 .byte 0
216 0008 01 .byte 1
ARM GAS /tmp/ccHSpkP2.s page 11
217 0009 02 .byte 2
218 000a 03 .byte 3
219 000b 04 .byte 4
220 000c 06 .byte 6
221 000d 07 .byte 7
222 000e 08 .byte 8
223 000f 09 .byte 9
224 .section .rodata.APBPrescTable,"a"
225 .align 2
228 APBPrescTable:
229 0000 00 .byte 0
230 0001 00 .byte 0
231 0002 00 .byte 0
232 0003 00 .byte 0
233 0004 01 .byte 1
234 0005 02 .byte 2
235 0006 03 .byte 3
236 0007 04 .byte 4
237 .text
238 .Letext0:
239 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h"
240 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h"
241 .file 4 "Drivers/CMSIS/Include/core_cm3.h"
242 .file 5 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h"
243 .file 6 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h"
244 .file 7 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h"
245 .file 8 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h"
ARM GAS /tmp/ccHSpkP2.s page 12
DEFINED SYMBOLS
*ABS*:0000000000000000 system_stm32f1xx.c
/tmp/ccHSpkP2.s:16 .text.SystemInit:0000000000000000 $t
/tmp/ccHSpkP2.s:24 .text.SystemInit:0000000000000000 SystemInit
/tmp/ccHSpkP2.s:38 .text.SystemCoreClockUpdate:0000000000000000 $t
/tmp/ccHSpkP2.s:45 .text.SystemCoreClockUpdate:0000000000000000 SystemCoreClockUpdate
/tmp/ccHSpkP2.s:184 .text.SystemCoreClockUpdate:0000000000000080 $d
/tmp/ccHSpkP2.s:228 .rodata.APBPrescTable:0000000000000000 APBPrescTable
/tmp/ccHSpkP2.s:207 .rodata.AHBPrescTable:0000000000000000 AHBPrescTable
/tmp/ccHSpkP2.s:200 .data.SystemCoreClock:0000000000000000 SystemCoreClock
/tmp/ccHSpkP2.s:196 .data.SystemCoreClock:0000000000000000 $d
/tmp/ccHSpkP2.s:203 .rodata.AHBPrescTable:0000000000000000 $d
/tmp/ccHSpkP2.s:225 .rodata.APBPrescTable:0000000000000000 $d
NO UNDEFINED SYMBOLS

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rusci-firmware/build/system_stm32f1xx.o Normal file
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