Demo blink sketch for first test
This commit is contained in:
Moritz Martinius
525
rusci-firmware/build/stm32f1xx_hal_msp.lst
Normal file
525
rusci-firmware/build/stm32f1xx_hal_msp.lst
Normal file
@@ -0,0 +1,525 @@
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ARM GAS /tmp/ccEGCTiT.s page 1
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1 .cpu cortex-m3
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2 .eabi_attribute 20, 1
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3 .eabi_attribute 21, 1
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4 .eabi_attribute 23, 3
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5 .eabi_attribute 24, 1
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6 .eabi_attribute 25, 1
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7 .eabi_attribute 26, 1
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8 .eabi_attribute 30, 1
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9 .eabi_attribute 34, 1
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10 .eabi_attribute 18, 4
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11 .file "stm32f1xx_hal_msp.c"
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12 .text
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13 .Ltext0:
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14 .cfi_sections .debug_frame
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15 .section .text.HAL_MspInit,"ax",%progbits
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16 .align 1
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17 .global HAL_MspInit
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18 .arch armv7-m
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19 .syntax unified
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20 .thumb
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21 .thumb_func
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22 .fpu softvfp
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24 HAL_MspInit:
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25 .LFB65:
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26 .file 1 "Core/Src/stm32f1xx_hal_msp.c"
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1:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN Header */
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2:Core/Src/stm32f1xx_hal_msp.c **** /**
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3:Core/Src/stm32f1xx_hal_msp.c **** ******************************************************************************
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4:Core/Src/stm32f1xx_hal_msp.c **** * File Name : stm32f1xx_hal_msp.c
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5:Core/Src/stm32f1xx_hal_msp.c **** * Description : This file provides code for the MSP Initialization
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6:Core/Src/stm32f1xx_hal_msp.c **** * and de-Initialization codes.
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7:Core/Src/stm32f1xx_hal_msp.c **** ******************************************************************************
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8:Core/Src/stm32f1xx_hal_msp.c **** * @attention
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9:Core/Src/stm32f1xx_hal_msp.c **** *
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10:Core/Src/stm32f1xx_hal_msp.c **** * <h2><center>© Copyright (c) 2020 STMicroelectronics.
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11:Core/Src/stm32f1xx_hal_msp.c **** * All rights reserved.</center></h2>
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12:Core/Src/stm32f1xx_hal_msp.c **** *
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13:Core/Src/stm32f1xx_hal_msp.c **** * This software component is licensed by ST under BSD 3-Clause license,
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14:Core/Src/stm32f1xx_hal_msp.c **** * the "License"; You may not use this file except in compliance with the
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15:Core/Src/stm32f1xx_hal_msp.c **** * License. You may obtain a copy of the License at:
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16:Core/Src/stm32f1xx_hal_msp.c **** * opensource.org/licenses/BSD-3-Clause
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17:Core/Src/stm32f1xx_hal_msp.c **** *
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18:Core/Src/stm32f1xx_hal_msp.c **** ******************************************************************************
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19:Core/Src/stm32f1xx_hal_msp.c **** */
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20:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END Header */
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21:Core/Src/stm32f1xx_hal_msp.c ****
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22:Core/Src/stm32f1xx_hal_msp.c **** /* Includes ------------------------------------------------------------------*/
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23:Core/Src/stm32f1xx_hal_msp.c **** #include "main.h"
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24:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN Includes */
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25:Core/Src/stm32f1xx_hal_msp.c ****
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26:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END Includes */
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27:Core/Src/stm32f1xx_hal_msp.c ****
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28:Core/Src/stm32f1xx_hal_msp.c **** /* Private typedef -----------------------------------------------------------*/
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29:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN TD */
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30:Core/Src/stm32f1xx_hal_msp.c ****
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31:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END TD */
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32:Core/Src/stm32f1xx_hal_msp.c ****
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ARM GAS /tmp/ccEGCTiT.s page 2
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33:Core/Src/stm32f1xx_hal_msp.c **** /* Private define ------------------------------------------------------------*/
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34:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN Define */
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35:Core/Src/stm32f1xx_hal_msp.c ****
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36:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END Define */
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37:Core/Src/stm32f1xx_hal_msp.c ****
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38:Core/Src/stm32f1xx_hal_msp.c **** /* Private macro -------------------------------------------------------------*/
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39:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN Macro */
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40:Core/Src/stm32f1xx_hal_msp.c ****
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41:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END Macro */
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42:Core/Src/stm32f1xx_hal_msp.c ****
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43:Core/Src/stm32f1xx_hal_msp.c **** /* Private variables ---------------------------------------------------------*/
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44:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN PV */
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45:Core/Src/stm32f1xx_hal_msp.c ****
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46:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END PV */
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47:Core/Src/stm32f1xx_hal_msp.c ****
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48:Core/Src/stm32f1xx_hal_msp.c **** /* Private function prototypes -----------------------------------------------*/
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49:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN PFP */
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50:Core/Src/stm32f1xx_hal_msp.c ****
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51:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END PFP */
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52:Core/Src/stm32f1xx_hal_msp.c ****
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53:Core/Src/stm32f1xx_hal_msp.c **** /* External functions --------------------------------------------------------*/
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54:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN ExternalFunctions */
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55:Core/Src/stm32f1xx_hal_msp.c ****
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56:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END ExternalFunctions */
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57:Core/Src/stm32f1xx_hal_msp.c ****
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58:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN 0 */
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59:Core/Src/stm32f1xx_hal_msp.c ****
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60:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END 0 */
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61:Core/Src/stm32f1xx_hal_msp.c **** /**
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62:Core/Src/stm32f1xx_hal_msp.c **** * Initializes the Global MSP.
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63:Core/Src/stm32f1xx_hal_msp.c **** */
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64:Core/Src/stm32f1xx_hal_msp.c **** void HAL_MspInit(void)
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65:Core/Src/stm32f1xx_hal_msp.c **** {
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27 .loc 1 65 1 view -0
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28 .cfi_startproc
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29 @ args = 0, pretend = 0, frame = 8
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30 @ frame_needed = 0, uses_anonymous_args = 0
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31 @ link register save eliminated.
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32 0000 82B0 sub sp, sp, #8
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33 .LCFI0:
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34 .cfi_def_cfa_offset 8
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66:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN MspInit 0 */
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67:Core/Src/stm32f1xx_hal_msp.c ****
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68:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END MspInit 0 */
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69:Core/Src/stm32f1xx_hal_msp.c ****
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70:Core/Src/stm32f1xx_hal_msp.c **** __HAL_RCC_AFIO_CLK_ENABLE();
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35 .loc 1 70 3 view .LVU1
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36 .LBB2:
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37 .loc 1 70 3 view .LVU2
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38 .loc 1 70 3 view .LVU3
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39 0002 0E4B ldr r3, .L3
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40 0004 9A69 ldr r2, [r3, #24]
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41 0006 42F00102 orr r2, r2, #1
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42 000a 9A61 str r2, [r3, #24]
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43 .loc 1 70 3 view .LVU4
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44 000c 9A69 ldr r2, [r3, #24]
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45 000e 02F00102 and r2, r2, #1
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ARM GAS /tmp/ccEGCTiT.s page 3
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46 0012 0092 str r2, [sp]
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47 .loc 1 70 3 view .LVU5
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48 0014 009A ldr r2, [sp]
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49 .LBE2:
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71:Core/Src/stm32f1xx_hal_msp.c **** __HAL_RCC_PWR_CLK_ENABLE();
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50 .loc 1 71 3 view .LVU6
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51 .LBB3:
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52 .loc 1 71 3 view .LVU7
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53 .loc 1 71 3 view .LVU8
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54 0016 DA69 ldr r2, [r3, #28]
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55 0018 42F08052 orr r2, r2, #268435456
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56 001c DA61 str r2, [r3, #28]
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57 .loc 1 71 3 view .LVU9
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58 001e DB69 ldr r3, [r3, #28]
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59 0020 03F08053 and r3, r3, #268435456
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60 0024 0193 str r3, [sp, #4]
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61 .loc 1 71 3 view .LVU10
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62 0026 019B ldr r3, [sp, #4]
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63 .LBE3:
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72:Core/Src/stm32f1xx_hal_msp.c ****
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73:Core/Src/stm32f1xx_hal_msp.c **** /* System interrupt init*/
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74:Core/Src/stm32f1xx_hal_msp.c ****
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75:Core/Src/stm32f1xx_hal_msp.c **** /** DISABLE: JTAG-DP Disabled and SW-DP Disabled
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76:Core/Src/stm32f1xx_hal_msp.c **** */
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77:Core/Src/stm32f1xx_hal_msp.c **** __HAL_AFIO_REMAP_SWJ_DISABLE();
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64 .loc 1 77 3 view .LVU11
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65 .LBB4:
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66 .loc 1 77 3 view .LVU12
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67 0028 054A ldr r2, .L3+4
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68 002a 5368 ldr r3, [r2, #4]
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69 .LVL0:
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70 .loc 1 77 3 view .LVU13
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71 002c 23F0E063 bic r3, r3, #117440512
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72 .LVL1:
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73 .loc 1 77 3 view .LVU14
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74 0030 43F08063 orr r3, r3, #67108864
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75 .LVL2:
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76 .loc 1 77 3 view .LVU15
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77 0034 5360 str r3, [r2, #4]
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78 .LBE4:
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78:Core/Src/stm32f1xx_hal_msp.c ****
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79:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN MspInit 1 */
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80:Core/Src/stm32f1xx_hal_msp.c ****
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81:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END MspInit 1 */
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82:Core/Src/stm32f1xx_hal_msp.c **** }
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79 .loc 1 82 1 is_stmt 0 view .LVU16
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80 0036 02B0 add sp, sp, #8
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81 .LCFI1:
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82 .cfi_def_cfa_offset 0
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83 @ sp needed
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84 0038 7047 bx lr
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85 .L4:
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86 003a 00BF .align 2
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87 .L3:
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88 003c 00100240 .word 1073876992
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89 0040 00000140 .word 1073807360
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90 .cfi_endproc
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ARM GAS /tmp/ccEGCTiT.s page 4
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91 .LFE65:
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93 .section .text.HAL_CAN_MspInit,"ax",%progbits
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94 .align 1
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95 .global HAL_CAN_MspInit
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96 .syntax unified
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97 .thumb
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98 .thumb_func
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99 .fpu softvfp
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101 HAL_CAN_MspInit:
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102 .LVL3:
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103 .LFB66:
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83:Core/Src/stm32f1xx_hal_msp.c ****
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84:Core/Src/stm32f1xx_hal_msp.c **** /**
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85:Core/Src/stm32f1xx_hal_msp.c **** * @brief CAN MSP Initialization
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86:Core/Src/stm32f1xx_hal_msp.c **** * This function configures the hardware resources used in this example
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87:Core/Src/stm32f1xx_hal_msp.c **** * @param hcan: CAN handle pointer
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88:Core/Src/stm32f1xx_hal_msp.c **** * @retval None
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89:Core/Src/stm32f1xx_hal_msp.c **** */
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90:Core/Src/stm32f1xx_hal_msp.c **** void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
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91:Core/Src/stm32f1xx_hal_msp.c **** {
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104 .loc 1 91 1 is_stmt 1 view -0
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105 .cfi_startproc
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106 @ args = 0, pretend = 0, frame = 24
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107 @ frame_needed = 0, uses_anonymous_args = 0
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108 .loc 1 91 1 is_stmt 0 view .LVU18
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109 0000 10B5 push {r4, lr}
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110 .LCFI2:
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111 .cfi_def_cfa_offset 8
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112 .cfi_offset 4, -8
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113 .cfi_offset 14, -4
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114 0002 86B0 sub sp, sp, #24
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115 .LCFI3:
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116 .cfi_def_cfa_offset 32
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92:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitTypeDef GPIO_InitStruct = {0};
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117 .loc 1 92 3 is_stmt 1 view .LVU19
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118 .loc 1 92 20 is_stmt 0 view .LVU20
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119 0004 0023 movs r3, #0
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120 0006 0293 str r3, [sp, #8]
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121 0008 0393 str r3, [sp, #12]
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122 000a 0493 str r3, [sp, #16]
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123 000c 0593 str r3, [sp, #20]
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93:Core/Src/stm32f1xx_hal_msp.c **** if(hcan->Instance==CAN1)
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124 .loc 1 93 3 is_stmt 1 view .LVU21
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125 .loc 1 93 10 is_stmt 0 view .LVU22
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126 000e 0268 ldr r2, [r0]
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127 .loc 1 93 5 view .LVU23
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128 0010 1A4B ldr r3, .L9
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129 0012 9A42 cmp r2, r3
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130 0014 01D0 beq .L8
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131 .LVL4:
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132 .L5:
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94:Core/Src/stm32f1xx_hal_msp.c **** {
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95:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN CAN1_MspInit 0 */
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96:Core/Src/stm32f1xx_hal_msp.c ****
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97:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END CAN1_MspInit 0 */
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98:Core/Src/stm32f1xx_hal_msp.c **** /* Peripheral clock enable */
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99:Core/Src/stm32f1xx_hal_msp.c **** __HAL_RCC_CAN1_CLK_ENABLE();
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ARM GAS /tmp/ccEGCTiT.s page 5
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100:Core/Src/stm32f1xx_hal_msp.c ****
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101:Core/Src/stm32f1xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE();
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102:Core/Src/stm32f1xx_hal_msp.c **** /**CAN GPIO Configuration
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103:Core/Src/stm32f1xx_hal_msp.c **** PB8 ------> CAN_RX
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104:Core/Src/stm32f1xx_hal_msp.c **** PB9 ------> CAN_TX
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105:Core/Src/stm32f1xx_hal_msp.c **** */
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106:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Pin = GPIO_PIN_8;
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107:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
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108:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
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109:Core/Src/stm32f1xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
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110:Core/Src/stm32f1xx_hal_msp.c ****
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111:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Pin = GPIO_PIN_9;
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112:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
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113:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
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114:Core/Src/stm32f1xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
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115:Core/Src/stm32f1xx_hal_msp.c ****
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116:Core/Src/stm32f1xx_hal_msp.c **** __HAL_AFIO_REMAP_CAN1_2();
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117:Core/Src/stm32f1xx_hal_msp.c ****
|
||||
118:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN CAN1_MspInit 1 */
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119:Core/Src/stm32f1xx_hal_msp.c ****
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||||
120:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END CAN1_MspInit 1 */
|
||||
121:Core/Src/stm32f1xx_hal_msp.c **** }
|
||||
122:Core/Src/stm32f1xx_hal_msp.c ****
|
||||
123:Core/Src/stm32f1xx_hal_msp.c **** }
|
||||
133 .loc 1 123 1 view .LVU24
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||||
134 0016 06B0 add sp, sp, #24
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135 .LCFI4:
|
||||
136 .cfi_remember_state
|
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137 .cfi_def_cfa_offset 8
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138 @ sp needed
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139 0018 10BD pop {r4, pc}
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140 .LVL5:
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||||
141 .L8:
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||||
142 .LCFI5:
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||||
143 .cfi_restore_state
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||||
99:Core/Src/stm32f1xx_hal_msp.c ****
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||||
144 .loc 1 99 5 is_stmt 1 view .LVU25
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145 .LBB5:
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||||
99:Core/Src/stm32f1xx_hal_msp.c ****
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||||
146 .loc 1 99 5 view .LVU26
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||||
99:Core/Src/stm32f1xx_hal_msp.c ****
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||||
147 .loc 1 99 5 view .LVU27
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||||
148 001a 03F5D633 add r3, r3, #109568
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149 001e DA69 ldr r2, [r3, #28]
|
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150 0020 42F00072 orr r2, r2, #33554432
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||||
151 0024 DA61 str r2, [r3, #28]
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99:Core/Src/stm32f1xx_hal_msp.c ****
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||||
152 .loc 1 99 5 view .LVU28
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153 0026 DA69 ldr r2, [r3, #28]
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154 0028 02F00072 and r2, r2, #33554432
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||||
155 002c 0092 str r2, [sp]
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||||
99:Core/Src/stm32f1xx_hal_msp.c ****
|
||||
156 .loc 1 99 5 view .LVU29
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||||
157 002e 009A ldr r2, [sp]
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158 .LBE5:
|
||||
101:Core/Src/stm32f1xx_hal_msp.c **** /**CAN GPIO Configuration
|
||||
159 .loc 1 101 5 view .LVU30
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ARM GAS /tmp/ccEGCTiT.s page 6
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||||
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160 .LBB6:
|
||||
101:Core/Src/stm32f1xx_hal_msp.c **** /**CAN GPIO Configuration
|
||||
161 .loc 1 101 5 view .LVU31
|
||||
101:Core/Src/stm32f1xx_hal_msp.c **** /**CAN GPIO Configuration
|
||||
162 .loc 1 101 5 view .LVU32
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||||
163 0030 9A69 ldr r2, [r3, #24]
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164 0032 42F00802 orr r2, r2, #8
|
||||
165 0036 9A61 str r2, [r3, #24]
|
||||
101:Core/Src/stm32f1xx_hal_msp.c **** /**CAN GPIO Configuration
|
||||
166 .loc 1 101 5 view .LVU33
|
||||
167 0038 9B69 ldr r3, [r3, #24]
|
||||
168 003a 03F00803 and r3, r3, #8
|
||||
169 003e 0193 str r3, [sp, #4]
|
||||
101:Core/Src/stm32f1xx_hal_msp.c **** /**CAN GPIO Configuration
|
||||
170 .loc 1 101 5 view .LVU34
|
||||
171 0040 019B ldr r3, [sp, #4]
|
||||
172 .LBE6:
|
||||
106:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
|
||||
173 .loc 1 106 5 view .LVU35
|
||||
106:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
|
||||
174 .loc 1 106 25 is_stmt 0 view .LVU36
|
||||
175 0042 4FF48073 mov r3, #256
|
||||
176 0046 0293 str r3, [sp, #8]
|
||||
107:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
177 .loc 1 107 5 is_stmt 1 view .LVU37
|
||||
108:Core/Src/stm32f1xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
||||
178 .loc 1 108 5 view .LVU38
|
||||
109:Core/Src/stm32f1xx_hal_msp.c ****
|
||||
179 .loc 1 109 5 view .LVU39
|
||||
180 0048 0D4C ldr r4, .L9+4
|
||||
181 004a 02A9 add r1, sp, #8
|
||||
182 004c 2046 mov r0, r4
|
||||
183 .LVL6:
|
||||
109:Core/Src/stm32f1xx_hal_msp.c ****
|
||||
184 .loc 1 109 5 is_stmt 0 view .LVU40
|
||||
185 004e FFF7FEFF bl HAL_GPIO_Init
|
||||
186 .LVL7:
|
||||
111:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||
187 .loc 1 111 5 is_stmt 1 view .LVU41
|
||||
111:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||
188 .loc 1 111 25 is_stmt 0 view .LVU42
|
||||
189 0052 4FF40073 mov r3, #512
|
||||
190 0056 0293 str r3, [sp, #8]
|
||||
112:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
|
||||
191 .loc 1 112 5 is_stmt 1 view .LVU43
|
||||
112:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
|
||||
192 .loc 1 112 26 is_stmt 0 view .LVU44
|
||||
193 0058 0223 movs r3, #2
|
||||
194 005a 0393 str r3, [sp, #12]
|
||||
113:Core/Src/stm32f1xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
||||
195 .loc 1 113 5 is_stmt 1 view .LVU45
|
||||
113:Core/Src/stm32f1xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
||||
196 .loc 1 113 27 is_stmt 0 view .LVU46
|
||||
197 005c 0323 movs r3, #3
|
||||
198 005e 0593 str r3, [sp, #20]
|
||||
114:Core/Src/stm32f1xx_hal_msp.c ****
|
||||
199 .loc 1 114 5 is_stmt 1 view .LVU47
|
||||
ARM GAS /tmp/ccEGCTiT.s page 7
|
||||
|
||||
|
||||
200 0060 02A9 add r1, sp, #8
|
||||
201 0062 2046 mov r0, r4
|
||||
202 0064 FFF7FEFF bl HAL_GPIO_Init
|
||||
203 .LVL8:
|
||||
116:Core/Src/stm32f1xx_hal_msp.c ****
|
||||
204 .loc 1 116 5 view .LVU48
|
||||
205 .LBB7:
|
||||
116:Core/Src/stm32f1xx_hal_msp.c ****
|
||||
206 .loc 1 116 5 view .LVU49
|
||||
207 0068 064A ldr r2, .L9+8
|
||||
208 006a 5368 ldr r3, [r2, #4]
|
||||
209 .LVL9:
|
||||
116:Core/Src/stm32f1xx_hal_msp.c ****
|
||||
210 .loc 1 116 5 view .LVU50
|
||||
211 006c 23F4C043 bic r3, r3, #24576
|
||||
212 .LVL10:
|
||||
116:Core/Src/stm32f1xx_hal_msp.c ****
|
||||
213 .loc 1 116 5 view .LVU51
|
||||
116:Core/Src/stm32f1xx_hal_msp.c ****
|
||||
214 .loc 1 116 5 view .LVU52
|
||||
215 0070 43F0E063 orr r3, r3, #117440512
|
||||
216 .LVL11:
|
||||
116:Core/Src/stm32f1xx_hal_msp.c ****
|
||||
217 .loc 1 116 5 is_stmt 0 view .LVU53
|
||||
218 0074 43F48043 orr r3, r3, #16384
|
||||
219 .LVL12:
|
||||
116:Core/Src/stm32f1xx_hal_msp.c ****
|
||||
220 .loc 1 116 5 is_stmt 1 view .LVU54
|
||||
221 0078 5360 str r3, [r2, #4]
|
||||
222 .LBE7:
|
||||
223 .loc 1 123 1 is_stmt 0 view .LVU55
|
||||
224 007a CCE7 b .L5
|
||||
225 .L10:
|
||||
226 .align 2
|
||||
227 .L9:
|
||||
228 007c 00640040 .word 1073767424
|
||||
229 0080 000C0140 .word 1073810432
|
||||
230 0084 00000140 .word 1073807360
|
||||
231 .cfi_endproc
|
||||
232 .LFE66:
|
||||
234 .section .text.HAL_CAN_MspDeInit,"ax",%progbits
|
||||
235 .align 1
|
||||
236 .global HAL_CAN_MspDeInit
|
||||
237 .syntax unified
|
||||
238 .thumb
|
||||
239 .thumb_func
|
||||
240 .fpu softvfp
|
||||
242 HAL_CAN_MspDeInit:
|
||||
243 .LVL13:
|
||||
244 .LFB67:
|
||||
124:Core/Src/stm32f1xx_hal_msp.c ****
|
||||
125:Core/Src/stm32f1xx_hal_msp.c **** /**
|
||||
126:Core/Src/stm32f1xx_hal_msp.c **** * @brief CAN MSP De-Initialization
|
||||
127:Core/Src/stm32f1xx_hal_msp.c **** * This function freeze the hardware resources used in this example
|
||||
128:Core/Src/stm32f1xx_hal_msp.c **** * @param hcan: CAN handle pointer
|
||||
129:Core/Src/stm32f1xx_hal_msp.c **** * @retval None
|
||||
130:Core/Src/stm32f1xx_hal_msp.c **** */
|
||||
ARM GAS /tmp/ccEGCTiT.s page 8
|
||||
|
||||
|
||||
131:Core/Src/stm32f1xx_hal_msp.c **** void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)
|
||||
132:Core/Src/stm32f1xx_hal_msp.c **** {
|
||||
245 .loc 1 132 1 is_stmt 1 view -0
|
||||
246 .cfi_startproc
|
||||
247 @ args = 0, pretend = 0, frame = 0
|
||||
248 @ frame_needed = 0, uses_anonymous_args = 0
|
||||
249 .loc 1 132 1 is_stmt 0 view .LVU57
|
||||
250 0000 08B5 push {r3, lr}
|
||||
251 .LCFI6:
|
||||
252 .cfi_def_cfa_offset 8
|
||||
253 .cfi_offset 3, -8
|
||||
254 .cfi_offset 14, -4
|
||||
133:Core/Src/stm32f1xx_hal_msp.c **** if(hcan->Instance==CAN1)
|
||||
255 .loc 1 133 3 is_stmt 1 view .LVU58
|
||||
256 .loc 1 133 10 is_stmt 0 view .LVU59
|
||||
257 0002 0268 ldr r2, [r0]
|
||||
258 .loc 1 133 5 view .LVU60
|
||||
259 0004 074B ldr r3, .L15
|
||||
260 0006 9A42 cmp r2, r3
|
||||
261 0008 00D0 beq .L14
|
||||
262 .LVL14:
|
||||
263 .L11:
|
||||
134:Core/Src/stm32f1xx_hal_msp.c **** {
|
||||
135:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN CAN1_MspDeInit 0 */
|
||||
136:Core/Src/stm32f1xx_hal_msp.c ****
|
||||
137:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END CAN1_MspDeInit 0 */
|
||||
138:Core/Src/stm32f1xx_hal_msp.c **** /* Peripheral clock disable */
|
||||
139:Core/Src/stm32f1xx_hal_msp.c **** __HAL_RCC_CAN1_CLK_DISABLE();
|
||||
140:Core/Src/stm32f1xx_hal_msp.c ****
|
||||
141:Core/Src/stm32f1xx_hal_msp.c **** /**CAN GPIO Configuration
|
||||
142:Core/Src/stm32f1xx_hal_msp.c **** PB8 ------> CAN_RX
|
||||
143:Core/Src/stm32f1xx_hal_msp.c **** PB9 ------> CAN_TX
|
||||
144:Core/Src/stm32f1xx_hal_msp.c **** */
|
||||
145:Core/Src/stm32f1xx_hal_msp.c **** HAL_GPIO_DeInit(GPIOB, GPIO_PIN_8|GPIO_PIN_9);
|
||||
146:Core/Src/stm32f1xx_hal_msp.c ****
|
||||
147:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN CAN1_MspDeInit 1 */
|
||||
148:Core/Src/stm32f1xx_hal_msp.c ****
|
||||
149:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END CAN1_MspDeInit 1 */
|
||||
150:Core/Src/stm32f1xx_hal_msp.c **** }
|
||||
151:Core/Src/stm32f1xx_hal_msp.c ****
|
||||
152:Core/Src/stm32f1xx_hal_msp.c **** }
|
||||
264 .loc 1 152 1 view .LVU61
|
||||
265 000a 08BD pop {r3, pc}
|
||||
266 .LVL15:
|
||||
267 .L14:
|
||||
139:Core/Src/stm32f1xx_hal_msp.c ****
|
||||
268 .loc 1 139 5 is_stmt 1 view .LVU62
|
||||
269 000c 064A ldr r2, .L15+4
|
||||
270 000e D369 ldr r3, [r2, #28]
|
||||
271 0010 23F00073 bic r3, r3, #33554432
|
||||
272 0014 D361 str r3, [r2, #28]
|
||||
145:Core/Src/stm32f1xx_hal_msp.c ****
|
||||
273 .loc 1 145 5 view .LVU63
|
||||
274 0016 4FF44071 mov r1, #768
|
||||
275 001a 0448 ldr r0, .L15+8
|
||||
276 .LVL16:
|
||||
145:Core/Src/stm32f1xx_hal_msp.c ****
|
||||
ARM GAS /tmp/ccEGCTiT.s page 9
|
||||
|
||||
|
||||
277 .loc 1 145 5 is_stmt 0 view .LVU64
|
||||
278 001c FFF7FEFF bl HAL_GPIO_DeInit
|
||||
279 .LVL17:
|
||||
280 .loc 1 152 1 view .LVU65
|
||||
281 0020 F3E7 b .L11
|
||||
282 .L16:
|
||||
283 0022 00BF .align 2
|
||||
284 .L15:
|
||||
285 0024 00640040 .word 1073767424
|
||||
286 0028 00100240 .word 1073876992
|
||||
287 002c 000C0140 .word 1073810432
|
||||
288 .cfi_endproc
|
||||
289 .LFE67:
|
||||
291 .text
|
||||
292 .Letext0:
|
||||
293 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h"
|
||||
294 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h"
|
||||
295 .file 4 "Drivers/CMSIS/Include/core_cm3.h"
|
||||
296 .file 5 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h"
|
||||
297 .file 6 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h"
|
||||
298 .file 7 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h"
|
||||
299 .file 8 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h"
|
||||
300 .file 9 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h"
|
||||
301 .file 10 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h"
|
||||
ARM GAS /tmp/ccEGCTiT.s page 10
|
||||
|
||||
|
||||
DEFINED SYMBOLS
|
||||
*ABS*:0000000000000000 stm32f1xx_hal_msp.c
|
||||
/tmp/ccEGCTiT.s:16 .text.HAL_MspInit:0000000000000000 $t
|
||||
/tmp/ccEGCTiT.s:24 .text.HAL_MspInit:0000000000000000 HAL_MspInit
|
||||
/tmp/ccEGCTiT.s:88 .text.HAL_MspInit:000000000000003c $d
|
||||
/tmp/ccEGCTiT.s:94 .text.HAL_CAN_MspInit:0000000000000000 $t
|
||||
/tmp/ccEGCTiT.s:101 .text.HAL_CAN_MspInit:0000000000000000 HAL_CAN_MspInit
|
||||
/tmp/ccEGCTiT.s:228 .text.HAL_CAN_MspInit:000000000000007c $d
|
||||
/tmp/ccEGCTiT.s:235 .text.HAL_CAN_MspDeInit:0000000000000000 $t
|
||||
/tmp/ccEGCTiT.s:242 .text.HAL_CAN_MspDeInit:0000000000000000 HAL_CAN_MspDeInit
|
||||
/tmp/ccEGCTiT.s:285 .text.HAL_CAN_MspDeInit:0000000000000024 $d
|
||||
|
||||
UNDEFINED SYMBOLS
|
||||
HAL_GPIO_Init
|
||||
HAL_GPIO_DeInit
|
||||
Reference in New Issue
Block a user