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Demo blink sketch for first test

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This commit is contained in:
Moritz Martinius
2020-11-07 12:48:40 +01:00
parent 376a9bee91
commit 66bea6372f
969 changed files with 615038 additions and 0 deletions
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rusci-firmware/build/system_stm32f1xx.lst Normal file
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ARM GAS /tmp/ccHSpkP2.s page 1
1 .cpu cortex-m3
2 .eabi_attribute 20, 1
3 .eabi_attribute 21, 1
4 .eabi_attribute 23, 3
5 .eabi_attribute 24, 1
6 .eabi_attribute 25, 1
7 .eabi_attribute 26, 1
8 .eabi_attribute 30, 1
9 .eabi_attribute 34, 1
10 .eabi_attribute 18, 4
11 .file "system_stm32f1xx.c"
12 .text
13 .Ltext0:
14 .cfi_sections .debug_frame
15 .section .text.SystemInit,"ax",%progbits
16 .align 1
17 .global SystemInit
18 .arch armv7-m
19 .syntax unified
20 .thumb
21 .thumb_func
22 .fpu softvfp
24 SystemInit:
25 .LFB65:
26 .file 1 "Core/Src/system_stm32f1xx.c"
1:Core/Src/system_stm32f1xx.c **** /**
2:Core/Src/system_stm32f1xx.c **** ******************************************************************************
3:Core/Src/system_stm32f1xx.c **** * @file system_stm32f1xx.c
4:Core/Src/system_stm32f1xx.c **** * @author MCD Application Team
5:Core/Src/system_stm32f1xx.c **** * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
6:Core/Src/system_stm32f1xx.c **** *
7:Core/Src/system_stm32f1xx.c **** * 1. This file provides two functions and one global variable to be called from
8:Core/Src/system_stm32f1xx.c **** * user application:
9:Core/Src/system_stm32f1xx.c **** * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
10:Core/Src/system_stm32f1xx.c **** * factors, AHB/APBx prescalers and Flash settings).
11:Core/Src/system_stm32f1xx.c **** * This function is called at startup just after reset and
12:Core/Src/system_stm32f1xx.c **** * before branch to main program. This call is made inside
13:Core/Src/system_stm32f1xx.c **** * the "startup_stm32f1xx_xx.s" file.
14:Core/Src/system_stm32f1xx.c **** *
15:Core/Src/system_stm32f1xx.c **** * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
16:Core/Src/system_stm32f1xx.c **** * by the user application to setup the SysTick
17:Core/Src/system_stm32f1xx.c **** * timer or configure other parameters.
18:Core/Src/system_stm32f1xx.c **** *
19:Core/Src/system_stm32f1xx.c **** * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
20:Core/Src/system_stm32f1xx.c **** * be called whenever the core clock is changed
21:Core/Src/system_stm32f1xx.c **** * during program execution.
22:Core/Src/system_stm32f1xx.c **** *
23:Core/Src/system_stm32f1xx.c **** * 2. After each device reset the HSI (8 MHz) is used as system clock source.
24:Core/Src/system_stm32f1xx.c **** * Then SystemInit() function is called, in "startup_stm32f1xx_xx.s" file, to
25:Core/Src/system_stm32f1xx.c **** * configure the system clock before to branch to main program.
26:Core/Src/system_stm32f1xx.c **** *
27:Core/Src/system_stm32f1xx.c **** * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on
28:Core/Src/system_stm32f1xx.c **** * the product used), refer to "HSE_VALUE".
29:Core/Src/system_stm32f1xx.c **** * When HSE is used as system clock source, directly or through PLL, and you
30:Core/Src/system_stm32f1xx.c **** * are using different crystal you have to adapt the HSE value to your own
31:Core/Src/system_stm32f1xx.c **** * configuration.
32:Core/Src/system_stm32f1xx.c **** *
ARM GAS /tmp/ccHSpkP2.s page 2
33:Core/Src/system_stm32f1xx.c **** ******************************************************************************
34:Core/Src/system_stm32f1xx.c **** * @attention
35:Core/Src/system_stm32f1xx.c **** *
36:Core/Src/system_stm32f1xx.c **** * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
37:Core/Src/system_stm32f1xx.c **** * All rights reserved.</center></h2>
38:Core/Src/system_stm32f1xx.c **** *
39:Core/Src/system_stm32f1xx.c **** * This software component is licensed by ST under BSD 3-Clause license,
40:Core/Src/system_stm32f1xx.c **** * the "License"; You may not use this file except in compliance with the
41:Core/Src/system_stm32f1xx.c **** * License. You may obtain a copy of the License at:
42:Core/Src/system_stm32f1xx.c **** * opensource.org/licenses/BSD-3-Clause
43:Core/Src/system_stm32f1xx.c **** *
44:Core/Src/system_stm32f1xx.c **** ******************************************************************************
45:Core/Src/system_stm32f1xx.c **** */
46:Core/Src/system_stm32f1xx.c ****
47:Core/Src/system_stm32f1xx.c **** /** @addtogroup CMSIS
48:Core/Src/system_stm32f1xx.c **** * @{
49:Core/Src/system_stm32f1xx.c **** */
50:Core/Src/system_stm32f1xx.c ****
51:Core/Src/system_stm32f1xx.c **** /** @addtogroup stm32f1xx_system
52:Core/Src/system_stm32f1xx.c **** * @{
53:Core/Src/system_stm32f1xx.c **** */
54:Core/Src/system_stm32f1xx.c ****
55:Core/Src/system_stm32f1xx.c **** /** @addtogroup STM32F1xx_System_Private_Includes
56:Core/Src/system_stm32f1xx.c **** * @{
57:Core/Src/system_stm32f1xx.c **** */
58:Core/Src/system_stm32f1xx.c ****
59:Core/Src/system_stm32f1xx.c **** #include "stm32f1xx.h"
60:Core/Src/system_stm32f1xx.c ****
61:Core/Src/system_stm32f1xx.c **** /**
62:Core/Src/system_stm32f1xx.c **** * @}
63:Core/Src/system_stm32f1xx.c **** */
64:Core/Src/system_stm32f1xx.c ****
65:Core/Src/system_stm32f1xx.c **** /** @addtogroup STM32F1xx_System_Private_TypesDefinitions
66:Core/Src/system_stm32f1xx.c **** * @{
67:Core/Src/system_stm32f1xx.c **** */
68:Core/Src/system_stm32f1xx.c ****
69:Core/Src/system_stm32f1xx.c **** /**
70:Core/Src/system_stm32f1xx.c **** * @}
71:Core/Src/system_stm32f1xx.c **** */
72:Core/Src/system_stm32f1xx.c ****
73:Core/Src/system_stm32f1xx.c **** /** @addtogroup STM32F1xx_System_Private_Defines
74:Core/Src/system_stm32f1xx.c **** * @{
75:Core/Src/system_stm32f1xx.c **** */
76:Core/Src/system_stm32f1xx.c ****
77:Core/Src/system_stm32f1xx.c **** #if !defined (HSE_VALUE)
78:Core/Src/system_stm32f1xx.c **** #define HSE_VALUE 8000000U /*!< Default value of the External oscillator in Hz.
79:Core/Src/system_stm32f1xx.c **** This value can be provided and adapted by the user
80:Core/Src/system_stm32f1xx.c **** #endif /* HSE_VALUE */
81:Core/Src/system_stm32f1xx.c ****
82:Core/Src/system_stm32f1xx.c **** #if !defined (HSI_VALUE)
83:Core/Src/system_stm32f1xx.c **** #define HSI_VALUE 8000000U /*!< Default value of the Internal oscillator in Hz.
84:Core/Src/system_stm32f1xx.c **** This value can be provided and adapted by the user
85:Core/Src/system_stm32f1xx.c **** #endif /* HSI_VALUE */
86:Core/Src/system_stm32f1xx.c ****
87:Core/Src/system_stm32f1xx.c **** /*!< Uncomment the following line if you need to use external SRAM */
88:Core/Src/system_stm32f1xx.c **** #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) ||
89:Core/Src/system_stm32f1xx.c **** /* #define DATA_IN_ExtSRAM */
ARM GAS /tmp/ccHSpkP2.s page 3
90:Core/Src/system_stm32f1xx.c **** #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
91:Core/Src/system_stm32f1xx.c ****
92:Core/Src/system_stm32f1xx.c **** /* Note: Following vector table addresses must be defined in line with linker
93:Core/Src/system_stm32f1xx.c **** configuration. */
94:Core/Src/system_stm32f1xx.c **** /*!< Uncomment the following line if you need to relocate the vector table
95:Core/Src/system_stm32f1xx.c **** anywhere in Flash or Sram, else the vector table is kept at the automatic
96:Core/Src/system_stm32f1xx.c **** remap of boot address selected */
97:Core/Src/system_stm32f1xx.c **** /* #define USER_VECT_TAB_ADDRESS */
98:Core/Src/system_stm32f1xx.c ****
99:Core/Src/system_stm32f1xx.c **** #if defined(USER_VECT_TAB_ADDRESS)
100:Core/Src/system_stm32f1xx.c **** /*!< Uncomment the following line if you need to relocate your vector Table
101:Core/Src/system_stm32f1xx.c **** in Sram else user remap will be done in Flash. */
102:Core/Src/system_stm32f1xx.c **** /* #define VECT_TAB_SRAM */
103:Core/Src/system_stm32f1xx.c **** #if defined(VECT_TAB_SRAM)
104:Core/Src/system_stm32f1xx.c **** #define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field.
105:Core/Src/system_stm32f1xx.c **** This value must be a multiple of 0x200. */
106:Core/Src/system_stm32f1xx.c **** #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
107:Core/Src/system_stm32f1xx.c **** This value must be a multiple of 0x200. */
108:Core/Src/system_stm32f1xx.c **** #else
109:Core/Src/system_stm32f1xx.c **** #define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
110:Core/Src/system_stm32f1xx.c **** This value must be a multiple of 0x200. */
111:Core/Src/system_stm32f1xx.c **** #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
112:Core/Src/system_stm32f1xx.c **** This value must be a multiple of 0x200. */
113:Core/Src/system_stm32f1xx.c **** #endif /* VECT_TAB_SRAM */
114:Core/Src/system_stm32f1xx.c **** #endif /* USER_VECT_TAB_ADDRESS */
115:Core/Src/system_stm32f1xx.c ****
116:Core/Src/system_stm32f1xx.c **** /******************************************************************************/
117:Core/Src/system_stm32f1xx.c ****
118:Core/Src/system_stm32f1xx.c **** /**
119:Core/Src/system_stm32f1xx.c **** * @}
120:Core/Src/system_stm32f1xx.c **** */
121:Core/Src/system_stm32f1xx.c ****
122:Core/Src/system_stm32f1xx.c **** /** @addtogroup STM32F1xx_System_Private_Macros
123:Core/Src/system_stm32f1xx.c **** * @{
124:Core/Src/system_stm32f1xx.c **** */
125:Core/Src/system_stm32f1xx.c ****
126:Core/Src/system_stm32f1xx.c **** /**
127:Core/Src/system_stm32f1xx.c **** * @}
128:Core/Src/system_stm32f1xx.c **** */
129:Core/Src/system_stm32f1xx.c ****
130:Core/Src/system_stm32f1xx.c **** /** @addtogroup STM32F1xx_System_Private_Variables
131:Core/Src/system_stm32f1xx.c **** * @{
132:Core/Src/system_stm32f1xx.c **** */
133:Core/Src/system_stm32f1xx.c ****
134:Core/Src/system_stm32f1xx.c **** /* This variable is updated in three ways:
135:Core/Src/system_stm32f1xx.c **** 1) by calling CMSIS function SystemCoreClockUpdate()
136:Core/Src/system_stm32f1xx.c **** 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
137:Core/Src/system_stm32f1xx.c **** 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
138:Core/Src/system_stm32f1xx.c **** Note: If you use this function to configure the system clock; then there
139:Core/Src/system_stm32f1xx.c **** is no need to call the 2 first functions listed above, since SystemCoreClock
140:Core/Src/system_stm32f1xx.c **** variable is updated automatically.
141:Core/Src/system_stm32f1xx.c **** */
142:Core/Src/system_stm32f1xx.c **** uint32_t SystemCoreClock = 16000000;
143:Core/Src/system_stm32f1xx.c **** const uint8_t AHBPrescTable[16U] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
144:Core/Src/system_stm32f1xx.c **** const uint8_t APBPrescTable[8U] = {0, 0, 0, 0, 1, 2, 3, 4};
145:Core/Src/system_stm32f1xx.c ****
146:Core/Src/system_stm32f1xx.c **** /**
ARM GAS /tmp/ccHSpkP2.s page 4
147:Core/Src/system_stm32f1xx.c **** * @}
148:Core/Src/system_stm32f1xx.c **** */
149:Core/Src/system_stm32f1xx.c ****
150:Core/Src/system_stm32f1xx.c **** /** @addtogroup STM32F1xx_System_Private_FunctionPrototypes
151:Core/Src/system_stm32f1xx.c **** * @{
152:Core/Src/system_stm32f1xx.c **** */
153:Core/Src/system_stm32f1xx.c ****
154:Core/Src/system_stm32f1xx.c **** #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) ||
155:Core/Src/system_stm32f1xx.c **** #ifdef DATA_IN_ExtSRAM
156:Core/Src/system_stm32f1xx.c **** static void SystemInit_ExtMemCtl(void);
157:Core/Src/system_stm32f1xx.c **** #endif /* DATA_IN_ExtSRAM */
158:Core/Src/system_stm32f1xx.c **** #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
159:Core/Src/system_stm32f1xx.c ****
160:Core/Src/system_stm32f1xx.c **** /**
161:Core/Src/system_stm32f1xx.c **** * @}
162:Core/Src/system_stm32f1xx.c **** */
163:Core/Src/system_stm32f1xx.c ****
164:Core/Src/system_stm32f1xx.c **** /** @addtogroup STM32F1xx_System_Private_Functions
165:Core/Src/system_stm32f1xx.c **** * @{
166:Core/Src/system_stm32f1xx.c **** */
167:Core/Src/system_stm32f1xx.c ****
168:Core/Src/system_stm32f1xx.c **** /**
169:Core/Src/system_stm32f1xx.c **** * @brief Setup the microcontroller system
170:Core/Src/system_stm32f1xx.c **** * Initialize the Embedded Flash Interface, the PLL and update the
171:Core/Src/system_stm32f1xx.c **** * SystemCoreClock variable.
172:Core/Src/system_stm32f1xx.c **** * @note This function should be used only after reset.
173:Core/Src/system_stm32f1xx.c **** * @param None
174:Core/Src/system_stm32f1xx.c **** * @retval None
175:Core/Src/system_stm32f1xx.c **** */
176:Core/Src/system_stm32f1xx.c **** void SystemInit (void)
177:Core/Src/system_stm32f1xx.c **** {
27 .loc 1 177 1 view -0
28 .cfi_startproc
29 @ args = 0, pretend = 0, frame = 0
30 @ frame_needed = 0, uses_anonymous_args = 0
31 @ link register save eliminated.
178:Core/Src/system_stm32f1xx.c **** #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) ||
179:Core/Src/system_stm32f1xx.c **** #ifdef DATA_IN_ExtSRAM
180:Core/Src/system_stm32f1xx.c **** SystemInit_ExtMemCtl();
181:Core/Src/system_stm32f1xx.c **** #endif /* DATA_IN_ExtSRAM */
182:Core/Src/system_stm32f1xx.c **** #endif
183:Core/Src/system_stm32f1xx.c ****
184:Core/Src/system_stm32f1xx.c **** /* Configure the Vector Table location -------------------------------------*/
185:Core/Src/system_stm32f1xx.c **** #if defined(USER_VECT_TAB_ADDRESS)
186:Core/Src/system_stm32f1xx.c **** SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM.
187:Core/Src/system_stm32f1xx.c **** #endif /* USER_VECT_TAB_ADDRESS */
188:Core/Src/system_stm32f1xx.c **** }
32 .loc 1 188 1 view .LVU1
33 0000 7047 bx lr
34 .cfi_endproc
35 .LFE65:
37 .section .text.SystemCoreClockUpdate,"ax",%progbits
38 .align 1
39 .global SystemCoreClockUpdate
40 .syntax unified
41 .thumb
42 .thumb_func
ARM GAS /tmp/ccHSpkP2.s page 5
43 .fpu softvfp
45 SystemCoreClockUpdate:
46 .LFB66:
189:Core/Src/system_stm32f1xx.c ****
190:Core/Src/system_stm32f1xx.c **** /**
191:Core/Src/system_stm32f1xx.c **** * @brief Update SystemCoreClock variable according to Clock Register Values.
192:Core/Src/system_stm32f1xx.c **** * The SystemCoreClock variable contains the core clock (HCLK), it can
193:Core/Src/system_stm32f1xx.c **** * be used by the user application to setup the SysTick timer or configure
194:Core/Src/system_stm32f1xx.c **** * other parameters.
195:Core/Src/system_stm32f1xx.c **** *
196:Core/Src/system_stm32f1xx.c **** * @note Each time the core clock (HCLK) changes, this function must be called
197:Core/Src/system_stm32f1xx.c **** * to update SystemCoreClock variable value. Otherwise, any configuration
198:Core/Src/system_stm32f1xx.c **** * based on this variable will be incorrect.
199:Core/Src/system_stm32f1xx.c **** *
200:Core/Src/system_stm32f1xx.c **** * @note - The system frequency computed by this function is not the real
201:Core/Src/system_stm32f1xx.c **** * frequency in the chip. It is calculated based on the predefined
202:Core/Src/system_stm32f1xx.c **** * constant and the selected clock source:
203:Core/Src/system_stm32f1xx.c **** *
204:Core/Src/system_stm32f1xx.c **** * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
205:Core/Src/system_stm32f1xx.c **** *
206:Core/Src/system_stm32f1xx.c **** * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
207:Core/Src/system_stm32f1xx.c **** *
208:Core/Src/system_stm32f1xx.c **** * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
209:Core/Src/system_stm32f1xx.c **** * or HSI_VALUE(*) multiplied by the PLL factors.
210:Core/Src/system_stm32f1xx.c **** *
211:Core/Src/system_stm32f1xx.c **** * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
212:Core/Src/system_stm32f1xx.c **** * 8 MHz) but the real value may vary depending on the variations
213:Core/Src/system_stm32f1xx.c **** * in voltage and temperature.
214:Core/Src/system_stm32f1xx.c **** *
215:Core/Src/system_stm32f1xx.c **** * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
216:Core/Src/system_stm32f1xx.c **** * 8 MHz or 25 MHz, depending on the product used), user has to ensure
217:Core/Src/system_stm32f1xx.c **** * that HSE_VALUE is same as the real frequency of the crystal used.
218:Core/Src/system_stm32f1xx.c **** * Otherwise, this function may have wrong result.
219:Core/Src/system_stm32f1xx.c **** *
220:Core/Src/system_stm32f1xx.c **** * - The result of this function could be not correct when using fractional
221:Core/Src/system_stm32f1xx.c **** * value for HSE crystal.
222:Core/Src/system_stm32f1xx.c **** * @param None
223:Core/Src/system_stm32f1xx.c **** * @retval None
224:Core/Src/system_stm32f1xx.c **** */
225:Core/Src/system_stm32f1xx.c **** void SystemCoreClockUpdate (void)
226:Core/Src/system_stm32f1xx.c **** {
47 .loc 1 226 1 view -0
48 .cfi_startproc
49 @ args = 0, pretend = 0, frame = 0
50 @ frame_needed = 0, uses_anonymous_args = 0
51 @ link register save eliminated.
227:Core/Src/system_stm32f1xx.c **** uint32_t tmp = 0U, pllmull = 0U, pllsource = 0U;
52 .loc 1 227 3 view .LVU3
53 .LVL0:
228:Core/Src/system_stm32f1xx.c ****
229:Core/Src/system_stm32f1xx.c **** #if defined(STM32F105xC) || defined(STM32F107xC)
230:Core/Src/system_stm32f1xx.c **** uint32_t prediv1source = 0U, prediv1factor = 0U, prediv2factor = 0U, pll2mull = 0U;
231:Core/Src/system_stm32f1xx.c **** #endif /* STM32F105xC */
232:Core/Src/system_stm32f1xx.c ****
233:Core/Src/system_stm32f1xx.c **** #if defined(STM32F100xB) || defined(STM32F100xE)
234:Core/Src/system_stm32f1xx.c **** uint32_t prediv1factor = 0U;
235:Core/Src/system_stm32f1xx.c **** #endif /* STM32F100xB or STM32F100xE */
ARM GAS /tmp/ccHSpkP2.s page 6
236:Core/Src/system_stm32f1xx.c ****
237:Core/Src/system_stm32f1xx.c **** /* Get SYSCLK source -------------------------------------------------------*/
238:Core/Src/system_stm32f1xx.c **** tmp = RCC->CFGR & RCC_CFGR_SWS;
54 .loc 1 238 3 view .LVU4
55 .loc 1 238 12 is_stmt 0 view .LVU5
56 0000 1F4B ldr r3, .L10
57 0002 5B68 ldr r3, [r3, #4]
58 .loc 1 238 7 view .LVU6
59 0004 03F00C03 and r3, r3, #12
60 .LVL1:
239:Core/Src/system_stm32f1xx.c ****
240:Core/Src/system_stm32f1xx.c **** switch (tmp)
61 .loc 1 240 3 is_stmt 1 view .LVU7
62 0008 042B cmp r3, #4
63 000a 14D0 beq .L3
64 000c 082B cmp r3, #8
65 000e 16D0 beq .L4
66 0010 1BB1 cbz r3, .L9
241:Core/Src/system_stm32f1xx.c **** {
242:Core/Src/system_stm32f1xx.c **** case 0x00U: /* HSI used as system clock */
243:Core/Src/system_stm32f1xx.c **** SystemCoreClock = HSI_VALUE;
244:Core/Src/system_stm32f1xx.c **** break;
245:Core/Src/system_stm32f1xx.c **** case 0x04U: /* HSE used as system clock */
246:Core/Src/system_stm32f1xx.c **** SystemCoreClock = HSE_VALUE;
247:Core/Src/system_stm32f1xx.c **** break;
248:Core/Src/system_stm32f1xx.c **** case 0x08U: /* PLL used as system clock */
249:Core/Src/system_stm32f1xx.c ****
250:Core/Src/system_stm32f1xx.c **** /* Get PLL clock source and multiplication factor ----------------------*/
251:Core/Src/system_stm32f1xx.c **** pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
252:Core/Src/system_stm32f1xx.c **** pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
253:Core/Src/system_stm32f1xx.c ****
254:Core/Src/system_stm32f1xx.c **** #if !defined(STM32F105xC) && !defined(STM32F107xC)
255:Core/Src/system_stm32f1xx.c **** pllmull = ( pllmull >> 18U) + 2U;
256:Core/Src/system_stm32f1xx.c ****
257:Core/Src/system_stm32f1xx.c **** if (pllsource == 0x00U)
258:Core/Src/system_stm32f1xx.c **** {
259:Core/Src/system_stm32f1xx.c **** /* HSI oscillator clock divided by 2 selected as PLL clock entry */
260:Core/Src/system_stm32f1xx.c **** SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;
261:Core/Src/system_stm32f1xx.c **** }
262:Core/Src/system_stm32f1xx.c **** else
263:Core/Src/system_stm32f1xx.c **** {
264:Core/Src/system_stm32f1xx.c **** #if defined(STM32F100xB) || defined(STM32F100xE)
265:Core/Src/system_stm32f1xx.c **** prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;
266:Core/Src/system_stm32f1xx.c **** /* HSE oscillator clock selected as PREDIV1 clock entry */
267:Core/Src/system_stm32f1xx.c **** SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
268:Core/Src/system_stm32f1xx.c **** #else
269:Core/Src/system_stm32f1xx.c **** /* HSE selected as PLL clock entry */
270:Core/Src/system_stm32f1xx.c **** if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
271:Core/Src/system_stm32f1xx.c **** {/* HSE oscillator clock divided by 2 */
272:Core/Src/system_stm32f1xx.c **** SystemCoreClock = (HSE_VALUE >> 1U) * pllmull;
273:Core/Src/system_stm32f1xx.c **** }
274:Core/Src/system_stm32f1xx.c **** else
275:Core/Src/system_stm32f1xx.c **** {
276:Core/Src/system_stm32f1xx.c **** SystemCoreClock = HSE_VALUE * pllmull;
277:Core/Src/system_stm32f1xx.c **** }
278:Core/Src/system_stm32f1xx.c **** #endif
279:Core/Src/system_stm32f1xx.c **** }
ARM GAS /tmp/ccHSpkP2.s page 7
280:Core/Src/system_stm32f1xx.c **** #else
281:Core/Src/system_stm32f1xx.c **** pllmull = pllmull >> 18U;
282:Core/Src/system_stm32f1xx.c ****
283:Core/Src/system_stm32f1xx.c **** if (pllmull != 0x0DU)
284:Core/Src/system_stm32f1xx.c **** {
285:Core/Src/system_stm32f1xx.c **** pllmull += 2U;
286:Core/Src/system_stm32f1xx.c **** }
287:Core/Src/system_stm32f1xx.c **** else
288:Core/Src/system_stm32f1xx.c **** { /* PLL multiplication factor = PLL input clock * 6.5 */
289:Core/Src/system_stm32f1xx.c **** pllmull = 13U / 2U;
290:Core/Src/system_stm32f1xx.c **** }
291:Core/Src/system_stm32f1xx.c ****
292:Core/Src/system_stm32f1xx.c **** if (pllsource == 0x00U)
293:Core/Src/system_stm32f1xx.c **** {
294:Core/Src/system_stm32f1xx.c **** /* HSI oscillator clock divided by 2 selected as PLL clock entry */
295:Core/Src/system_stm32f1xx.c **** SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;
296:Core/Src/system_stm32f1xx.c **** }
297:Core/Src/system_stm32f1xx.c **** else
298:Core/Src/system_stm32f1xx.c **** {/* PREDIV1 selected as PLL clock entry */
299:Core/Src/system_stm32f1xx.c ****
300:Core/Src/system_stm32f1xx.c **** /* Get PREDIV1 clock source and division factor */
301:Core/Src/system_stm32f1xx.c **** prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
302:Core/Src/system_stm32f1xx.c **** prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;
303:Core/Src/system_stm32f1xx.c ****
304:Core/Src/system_stm32f1xx.c **** if (prediv1source == 0U)
305:Core/Src/system_stm32f1xx.c **** {
306:Core/Src/system_stm32f1xx.c **** /* HSE oscillator clock selected as PREDIV1 clock entry */
307:Core/Src/system_stm32f1xx.c **** SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
308:Core/Src/system_stm32f1xx.c **** }
309:Core/Src/system_stm32f1xx.c **** else
310:Core/Src/system_stm32f1xx.c **** {/* PLL2 clock selected as PREDIV1 clock entry */
311:Core/Src/system_stm32f1xx.c ****
312:Core/Src/system_stm32f1xx.c **** /* Get PREDIV2 division factor and PLL2 multiplication factor */
313:Core/Src/system_stm32f1xx.c **** prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4U) + 1U;
314:Core/Src/system_stm32f1xx.c **** pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8U) + 2U;
315:Core/Src/system_stm32f1xx.c **** SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
316:Core/Src/system_stm32f1xx.c **** }
317:Core/Src/system_stm32f1xx.c **** }
318:Core/Src/system_stm32f1xx.c **** #endif /* STM32F105xC */
319:Core/Src/system_stm32f1xx.c **** break;
320:Core/Src/system_stm32f1xx.c ****
321:Core/Src/system_stm32f1xx.c **** default:
322:Core/Src/system_stm32f1xx.c **** SystemCoreClock = HSI_VALUE;
67 .loc 1 322 7 view .LVU8
68 .loc 1 322 23 is_stmt 0 view .LVU9
69 0012 1C4B ldr r3, .L10+4
70 .LVL2:
71 .loc 1 322 23 view .LVU10
72 0014 1C4A ldr r2, .L10+8
73 0016 1A60 str r2, [r3]
323:Core/Src/system_stm32f1xx.c **** break;
74 .loc 1 323 7 is_stmt 1 view .LVU11
75 0018 02E0 b .L6
76 .LVL3:
77 .L9:
243:Core/Src/system_stm32f1xx.c **** break;
78 .loc 1 243 7 view .LVU12
ARM GAS /tmp/ccHSpkP2.s page 8
243:Core/Src/system_stm32f1xx.c **** break;
79 .loc 1 243 23 is_stmt 0 view .LVU13
80 001a 1A4B ldr r3, .L10+4
81 .LVL4:
243:Core/Src/system_stm32f1xx.c **** break;
82 .loc 1 243 23 view .LVU14
83 001c 1A4A ldr r2, .L10+8
84 001e 1A60 str r2, [r3]
244:Core/Src/system_stm32f1xx.c **** case 0x04U: /* HSE used as system clock */
85 .loc 1 244 7 is_stmt 1 view .LVU15
86 .LVL5:
87 .L6:
324:Core/Src/system_stm32f1xx.c **** }
325:Core/Src/system_stm32f1xx.c ****
326:Core/Src/system_stm32f1xx.c **** /* Compute HCLK clock frequency ----------------*/
327:Core/Src/system_stm32f1xx.c **** /* Get HCLK prescaler */
328:Core/Src/system_stm32f1xx.c **** tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
88 .loc 1 328 3 view .LVU16
89 .loc 1 328 28 is_stmt 0 view .LVU17
90 0020 174B ldr r3, .L10
91 0022 5B68 ldr r3, [r3, #4]
92 .loc 1 328 52 view .LVU18
93 0024 C3F30313 ubfx r3, r3, #4, #4
94 .loc 1 328 22 view .LVU19
95 0028 184A ldr r2, .L10+12
96 002a D15C ldrb r1, [r2, r3] @ zero_extendqisi2
97 .LVL6:
329:Core/Src/system_stm32f1xx.c **** /* HCLK clock frequency */
330:Core/Src/system_stm32f1xx.c **** SystemCoreClock >>= tmp;
98 .loc 1 330 3 is_stmt 1 view .LVU20
99 .loc 1 330 19 is_stmt 0 view .LVU21
100 002c 154A ldr r2, .L10+4
101 002e 1368 ldr r3, [r2]
102 0030 CB40 lsrs r3, r3, r1
103 0032 1360 str r3, [r2]
331:Core/Src/system_stm32f1xx.c **** }
104 .loc 1 331 1 view .LVU22
105 0034 7047 bx lr
106 .LVL7:
107 .L3:
246:Core/Src/system_stm32f1xx.c **** break;
108 .loc 1 246 7 is_stmt 1 view .LVU23
246:Core/Src/system_stm32f1xx.c **** break;
109 .loc 1 246 23 is_stmt 0 view .LVU24
110 0036 134B ldr r3, .L10+4
111 .LVL8:
246:Core/Src/system_stm32f1xx.c **** break;
112 .loc 1 246 23 view .LVU25
113 0038 134A ldr r2, .L10+8
114 003a 1A60 str r2, [r3]
247:Core/Src/system_stm32f1xx.c **** case 0x08U: /* PLL used as system clock */
115 .loc 1 247 7 is_stmt 1 view .LVU26
116 003c F0E7 b .L6
117 .LVL9:
118 .L4:
251:Core/Src/system_stm32f1xx.c **** pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
119 .loc 1 251 7 view .LVU27
ARM GAS /tmp/ccHSpkP2.s page 9
251:Core/Src/system_stm32f1xx.c **** pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
120 .loc 1 251 20 is_stmt 0 view .LVU28
121 003e 104A ldr r2, .L10
122 0040 5368 ldr r3, [r2, #4]
123 .LVL10:
252:Core/Src/system_stm32f1xx.c ****
124 .loc 1 252 7 is_stmt 1 view .LVU29
252:Core/Src/system_stm32f1xx.c ****
125 .loc 1 252 22 is_stmt 0 view .LVU30
126 0042 5268 ldr r2, [r2, #4]
127 .LVL11:
255:Core/Src/system_stm32f1xx.c ****
128 .loc 1 255 7 is_stmt 1 view .LVU31
255:Core/Src/system_stm32f1xx.c ****
129 .loc 1 255 27 is_stmt 0 view .LVU32
130 0044 C3F38343 ubfx r3, r3, #18, #4
131 .LVL12:
255:Core/Src/system_stm32f1xx.c ****
132 .loc 1 255 15 view .LVU33
133 0048 0233 adds r3, r3, #2
134 .LVL13:
257:Core/Src/system_stm32f1xx.c **** {
135 .loc 1 257 7 is_stmt 1 view .LVU34
257:Core/Src/system_stm32f1xx.c **** {
136 .loc 1 257 10 is_stmt 0 view .LVU35
137 004a 12F4803F tst r2, #65536
138 004e 05D1 bne .L7
260:Core/Src/system_stm32f1xx.c **** }
139 .loc 1 260 9 is_stmt 1 view .LVU36
260:Core/Src/system_stm32f1xx.c **** }
140 .loc 1 260 45 is_stmt 0 view .LVU37
141 0050 0F4A ldr r2, .L10+16
142 .LVL14:
260:Core/Src/system_stm32f1xx.c **** }
143 .loc 1 260 45 view .LVU38
144 0052 02FB03F3 mul r3, r2, r3
145 .LVL15:
260:Core/Src/system_stm32f1xx.c **** }
146 .loc 1 260 25 view .LVU39
147 0056 0B4A ldr r2, .L10+4
148 0058 1360 str r3, [r2]
149 005a E1E7 b .L6
150 .LVL16:
151 .L7:
270:Core/Src/system_stm32f1xx.c **** {/* HSE oscillator clock divided by 2 */
152 .loc 1 270 9 is_stmt 1 view .LVU40
270:Core/Src/system_stm32f1xx.c **** {/* HSE oscillator clock divided by 2 */
153 .loc 1 270 17 is_stmt 0 view .LVU41
154 005c 084A ldr r2, .L10
155 .LVL17:
270:Core/Src/system_stm32f1xx.c **** {/* HSE oscillator clock divided by 2 */
156 .loc 1 270 17 view .LVU42
157 005e 5268 ldr r2, [r2, #4]
270:Core/Src/system_stm32f1xx.c **** {/* HSE oscillator clock divided by 2 */
158 .loc 1 270 12 view .LVU43
159 0060 12F4003F tst r2, #131072
160 0064 05D0 beq .L8
ARM GAS /tmp/ccHSpkP2.s page 10
272:Core/Src/system_stm32f1xx.c **** }
161 .loc 1 272 11 is_stmt 1 view .LVU44
272:Core/Src/system_stm32f1xx.c **** }
162 .loc 1 272 47 is_stmt 0 view .LVU45
163 0066 0A4A ldr r2, .L10+16
164 0068 02FB03F3 mul r3, r2, r3
165 .LVL18:
272:Core/Src/system_stm32f1xx.c **** }
166 .loc 1 272 27 view .LVU46
167 006c 054A ldr r2, .L10+4
168 006e 1360 str r3, [r2]
169 0070 D6E7 b .L6
170 .LVL19:
171 .L8:
276:Core/Src/system_stm32f1xx.c **** }
172 .loc 1 276 11 is_stmt 1 view .LVU47
276:Core/Src/system_stm32f1xx.c **** }
173 .loc 1 276 39 is_stmt 0 view .LVU48
174 0072 054A ldr r2, .L10+8
175 0074 02FB03F3 mul r3, r2, r3
176 .LVL20:
276:Core/Src/system_stm32f1xx.c **** }
177 .loc 1 276 27 view .LVU49
178 0078 024A ldr r2, .L10+4
179 007a 1360 str r3, [r2]
180 007c D0E7 b .L6
181 .L11:
182 007e 00BF .align 2
183 .L10:
184 0080 00100240 .word 1073876992
185 0084 00000000 .word .LANCHOR0
186 0088 00127A00 .word 8000000
187 008c 00000000 .word .LANCHOR1
188 0090 00093D00 .word 4000000
189 .cfi_endproc
190 .LFE66:
192 .global APBPrescTable
193 .global AHBPrescTable
194 .global SystemCoreClock
195 .section .data.SystemCoreClock,"aw"
196 .align 2
197 .set .LANCHOR0,. + 0
200 SystemCoreClock:
201 0000 0024F400 .word 16000000
202 .section .rodata.AHBPrescTable,"a"
203 .align 2
204 .set .LANCHOR1,. + 0
207 AHBPrescTable:
208 0000 00 .byte 0
209 0001 00 .byte 0
210 0002 00 .byte 0
211 0003 00 .byte 0
212 0004 00 .byte 0
213 0005 00 .byte 0
214 0006 00 .byte 0
215 0007 00 .byte 0
216 0008 01 .byte 1
ARM GAS /tmp/ccHSpkP2.s page 11
217 0009 02 .byte 2
218 000a 03 .byte 3
219 000b 04 .byte 4
220 000c 06 .byte 6
221 000d 07 .byte 7
222 000e 08 .byte 8
223 000f 09 .byte 9
224 .section .rodata.APBPrescTable,"a"
225 .align 2
228 APBPrescTable:
229 0000 00 .byte 0
230 0001 00 .byte 0
231 0002 00 .byte 0
232 0003 00 .byte 0
233 0004 01 .byte 1
234 0005 02 .byte 2
235 0006 03 .byte 3
236 0007 04 .byte 4
237 .text
238 .Letext0:
239 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h"
240 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h"
241 .file 4 "Drivers/CMSIS/Include/core_cm3.h"
242 .file 5 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h"
243 .file 6 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h"
244 .file 7 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h"
245 .file 8 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h"
ARM GAS /tmp/ccHSpkP2.s page 12
DEFINED SYMBOLS
*ABS*:0000000000000000 system_stm32f1xx.c
/tmp/ccHSpkP2.s:16 .text.SystemInit:0000000000000000 $t
/tmp/ccHSpkP2.s:24 .text.SystemInit:0000000000000000 SystemInit
/tmp/ccHSpkP2.s:38 .text.SystemCoreClockUpdate:0000000000000000 $t
/tmp/ccHSpkP2.s:45 .text.SystemCoreClockUpdate:0000000000000000 SystemCoreClockUpdate
/tmp/ccHSpkP2.s:184 .text.SystemCoreClockUpdate:0000000000000080 $d
/tmp/ccHSpkP2.s:228 .rodata.APBPrescTable:0000000000000000 APBPrescTable
/tmp/ccHSpkP2.s:207 .rodata.AHBPrescTable:0000000000000000 AHBPrescTable
/tmp/ccHSpkP2.s:200 .data.SystemCoreClock:0000000000000000 SystemCoreClock
/tmp/ccHSpkP2.s:196 .data.SystemCoreClock:0000000000000000 $d
/tmp/ccHSpkP2.s:203 .rodata.AHBPrescTable:0000000000000000 $d
/tmp/ccHSpkP2.s:225 .rodata.APBPrescTable:0000000000000000 $d
NO UNDEFINED SYMBOLS