ARM GAS /tmp/ccOMxQCE.s page 1 1 .cpu cortex-m3 2 .eabi_attribute 20, 1 3 .eabi_attribute 21, 1 4 .eabi_attribute 23, 3 5 .eabi_attribute 24, 1 6 .eabi_attribute 25, 1 7 .eabi_attribute 26, 1 8 .eabi_attribute 30, 1 9 .eabi_attribute 34, 1 10 .eabi_attribute 18, 4 11 .file "stm32f1xx_it.c" 12 .text 13 .Ltext0: 14 .cfi_sections .debug_frame 15 .section .text.NMI_Handler,"ax",%progbits 16 .align 1 17 .global NMI_Handler 18 .arch armv7-m 19 .syntax unified 20 .thumb 21 .thumb_func 22 .fpu softvfp 24 NMI_Handler: 25 .LFB65: 26 .file 1 "Core/Src/stm32f1xx_it.c" 1:Core/Src/stm32f1xx_it.c **** /* USER CODE BEGIN Header */ 2:Core/Src/stm32f1xx_it.c **** /** 3:Core/Src/stm32f1xx_it.c **** ****************************************************************************** 4:Core/Src/stm32f1xx_it.c **** * @file stm32f1xx_it.c 5:Core/Src/stm32f1xx_it.c **** * @brief Interrupt Service Routines. 6:Core/Src/stm32f1xx_it.c **** ****************************************************************************** 7:Core/Src/stm32f1xx_it.c **** * @attention 8:Core/Src/stm32f1xx_it.c **** * 9:Core/Src/stm32f1xx_it.c **** *

© Copyright (c) 2020 STMicroelectronics. 10:Core/Src/stm32f1xx_it.c **** * All rights reserved.

11:Core/Src/stm32f1xx_it.c **** * 12:Core/Src/stm32f1xx_it.c **** * This software component is licensed by ST under BSD 3-Clause license, 13:Core/Src/stm32f1xx_it.c **** * the "License"; You may not use this file except in compliance with the 14:Core/Src/stm32f1xx_it.c **** * License. You may obtain a copy of the License at: 15:Core/Src/stm32f1xx_it.c **** * opensource.org/licenses/BSD-3-Clause 16:Core/Src/stm32f1xx_it.c **** * 17:Core/Src/stm32f1xx_it.c **** ****************************************************************************** 18:Core/Src/stm32f1xx_it.c **** */ 19:Core/Src/stm32f1xx_it.c **** /* USER CODE END Header */ 20:Core/Src/stm32f1xx_it.c **** 21:Core/Src/stm32f1xx_it.c **** /* Includes ------------------------------------------------------------------*/ 22:Core/Src/stm32f1xx_it.c **** #include "main.h" 23:Core/Src/stm32f1xx_it.c **** #include "stm32f1xx_it.h" 24:Core/Src/stm32f1xx_it.c **** /* Private includes ----------------------------------------------------------*/ 25:Core/Src/stm32f1xx_it.c **** /* USER CODE BEGIN Includes */ 26:Core/Src/stm32f1xx_it.c **** /* USER CODE END Includes */ 27:Core/Src/stm32f1xx_it.c **** 28:Core/Src/stm32f1xx_it.c **** /* Private typedef -----------------------------------------------------------*/ 29:Core/Src/stm32f1xx_it.c **** /* USER CODE BEGIN TD */ 30:Core/Src/stm32f1xx_it.c **** 31:Core/Src/stm32f1xx_it.c **** /* USER CODE END TD */ 32:Core/Src/stm32f1xx_it.c **** ARM GAS /tmp/ccOMxQCE.s page 2 33:Core/Src/stm32f1xx_it.c **** /* Private define ------------------------------------------------------------*/ 34:Core/Src/stm32f1xx_it.c **** /* USER CODE BEGIN PD */ 35:Core/Src/stm32f1xx_it.c **** 36:Core/Src/stm32f1xx_it.c **** /* USER CODE END PD */ 37:Core/Src/stm32f1xx_it.c **** 38:Core/Src/stm32f1xx_it.c **** /* Private macro -------------------------------------------------------------*/ 39:Core/Src/stm32f1xx_it.c **** /* USER CODE BEGIN PM */ 40:Core/Src/stm32f1xx_it.c **** 41:Core/Src/stm32f1xx_it.c **** /* USER CODE END PM */ 42:Core/Src/stm32f1xx_it.c **** 43:Core/Src/stm32f1xx_it.c **** /* Private variables ---------------------------------------------------------*/ 44:Core/Src/stm32f1xx_it.c **** /* USER CODE BEGIN PV */ 45:Core/Src/stm32f1xx_it.c **** 46:Core/Src/stm32f1xx_it.c **** /* USER CODE END PV */ 47:Core/Src/stm32f1xx_it.c **** 48:Core/Src/stm32f1xx_it.c **** /* Private function prototypes -----------------------------------------------*/ 49:Core/Src/stm32f1xx_it.c **** /* USER CODE BEGIN PFP */ 50:Core/Src/stm32f1xx_it.c **** 51:Core/Src/stm32f1xx_it.c **** /* USER CODE END PFP */ 52:Core/Src/stm32f1xx_it.c **** 53:Core/Src/stm32f1xx_it.c **** /* Private user code ---------------------------------------------------------*/ 54:Core/Src/stm32f1xx_it.c **** /* USER CODE BEGIN 0 */ 55:Core/Src/stm32f1xx_it.c **** 56:Core/Src/stm32f1xx_it.c **** /* USER CODE END 0 */ 57:Core/Src/stm32f1xx_it.c **** 58:Core/Src/stm32f1xx_it.c **** /* External variables --------------------------------------------------------*/ 59:Core/Src/stm32f1xx_it.c **** 60:Core/Src/stm32f1xx_it.c **** /* USER CODE BEGIN EV */ 61:Core/Src/stm32f1xx_it.c **** 62:Core/Src/stm32f1xx_it.c **** /* USER CODE END EV */ 63:Core/Src/stm32f1xx_it.c **** 64:Core/Src/stm32f1xx_it.c **** /******************************************************************************/ 65:Core/Src/stm32f1xx_it.c **** /* Cortex-M3 Processor Interruption and Exception Handlers */ 66:Core/Src/stm32f1xx_it.c **** /******************************************************************************/ 67:Core/Src/stm32f1xx_it.c **** /** 68:Core/Src/stm32f1xx_it.c **** * @brief This function handles Non maskable interrupt. 69:Core/Src/stm32f1xx_it.c **** */ 70:Core/Src/stm32f1xx_it.c **** void NMI_Handler(void) 71:Core/Src/stm32f1xx_it.c **** { 27 .loc 1 71 1 view -0 28 .cfi_startproc 29 @ args = 0, pretend = 0, frame = 0 30 @ frame_needed = 0, uses_anonymous_args = 0 31 @ link register save eliminated. 72:Core/Src/stm32f1xx_it.c **** /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ 73:Core/Src/stm32f1xx_it.c **** 74:Core/Src/stm32f1xx_it.c **** /* USER CODE END NonMaskableInt_IRQn 0 */ 75:Core/Src/stm32f1xx_it.c **** /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ 76:Core/Src/stm32f1xx_it.c **** 77:Core/Src/stm32f1xx_it.c **** /* USER CODE END NonMaskableInt_IRQn 1 */ 78:Core/Src/stm32f1xx_it.c **** } 32 .loc 1 78 1 view .LVU1 33 0000 7047 bx lr 34 .cfi_endproc 35 .LFE65: 37 .section .text.HardFault_Handler,"ax",%progbits 38 .align 1 ARM GAS /tmp/ccOMxQCE.s page 3 39 .global HardFault_Handler 40 .syntax unified 41 .thumb 42 .thumb_func 43 .fpu softvfp 45 HardFault_Handler: 46 .LFB66: 79:Core/Src/stm32f1xx_it.c **** 80:Core/Src/stm32f1xx_it.c **** /** 81:Core/Src/stm32f1xx_it.c **** * @brief This function handles Hard fault interrupt. 82:Core/Src/stm32f1xx_it.c **** */ 83:Core/Src/stm32f1xx_it.c **** void HardFault_Handler(void) 84:Core/Src/stm32f1xx_it.c **** { 47 .loc 1 84 1 view -0 48 .cfi_startproc 49 @ Volatile: function does not return. 50 @ args = 0, pretend = 0, frame = 0 51 @ frame_needed = 0, uses_anonymous_args = 0 52 @ link register save eliminated. 53 .L3: 85:Core/Src/stm32f1xx_it.c **** /* USER CODE BEGIN HardFault_IRQn 0 */ 86:Core/Src/stm32f1xx_it.c **** 87:Core/Src/stm32f1xx_it.c **** /* USER CODE END HardFault_IRQn 0 */ 88:Core/Src/stm32f1xx_it.c **** while (1) 54 .loc 1 88 3 discriminator 1 view .LVU3 89:Core/Src/stm32f1xx_it.c **** { 90:Core/Src/stm32f1xx_it.c **** /* USER CODE BEGIN W1_HardFault_IRQn 0 */ 91:Core/Src/stm32f1xx_it.c **** /* USER CODE END W1_HardFault_IRQn 0 */ 92:Core/Src/stm32f1xx_it.c **** } 55 .loc 1 92 3 discriminator 1 view .LVU4 56 0000 FEE7 b .L3 57 .cfi_endproc 58 .LFE66: 60 .section .text.MemManage_Handler,"ax",%progbits 61 .align 1 62 .global MemManage_Handler 63 .syntax unified 64 .thumb 65 .thumb_func 66 .fpu softvfp 68 MemManage_Handler: 69 .LFB67: 93:Core/Src/stm32f1xx_it.c **** } 94:Core/Src/stm32f1xx_it.c **** 95:Core/Src/stm32f1xx_it.c **** /** 96:Core/Src/stm32f1xx_it.c **** * @brief This function handles Memory management fault. 97:Core/Src/stm32f1xx_it.c **** */ 98:Core/Src/stm32f1xx_it.c **** void MemManage_Handler(void) 99:Core/Src/stm32f1xx_it.c **** { 70 .loc 1 99 1 view -0 71 .cfi_startproc 72 @ Volatile: function does not return. 73 @ args = 0, pretend = 0, frame = 0 74 @ frame_needed = 0, uses_anonymous_args = 0 75 @ link register save eliminated. 76 .L5: 100:Core/Src/stm32f1xx_it.c **** /* USER CODE BEGIN MemoryManagement_IRQn 0 */ ARM GAS /tmp/ccOMxQCE.s page 4 101:Core/Src/stm32f1xx_it.c **** 102:Core/Src/stm32f1xx_it.c **** /* USER CODE END MemoryManagement_IRQn 0 */ 103:Core/Src/stm32f1xx_it.c **** while (1) 77 .loc 1 103 3 discriminator 1 view .LVU6 104:Core/Src/stm32f1xx_it.c **** { 105:Core/Src/stm32f1xx_it.c **** /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ 106:Core/Src/stm32f1xx_it.c **** /* USER CODE END W1_MemoryManagement_IRQn 0 */ 107:Core/Src/stm32f1xx_it.c **** } 78 .loc 1 107 3 discriminator 1 view .LVU7 79 0000 FEE7 b .L5 80 .cfi_endproc 81 .LFE67: 83 .section .text.BusFault_Handler,"ax",%progbits 84 .align 1 85 .global BusFault_Handler 86 .syntax unified 87 .thumb 88 .thumb_func 89 .fpu softvfp 91 BusFault_Handler: 92 .LFB68: 108:Core/Src/stm32f1xx_it.c **** } 109:Core/Src/stm32f1xx_it.c **** 110:Core/Src/stm32f1xx_it.c **** /** 111:Core/Src/stm32f1xx_it.c **** * @brief This function handles Prefetch fault, memory access fault. 112:Core/Src/stm32f1xx_it.c **** */ 113:Core/Src/stm32f1xx_it.c **** void BusFault_Handler(void) 114:Core/Src/stm32f1xx_it.c **** { 93 .loc 1 114 1 view -0 94 .cfi_startproc 95 @ Volatile: function does not return. 96 @ args = 0, pretend = 0, frame = 0 97 @ frame_needed = 0, uses_anonymous_args = 0 98 @ link register save eliminated. 99 .L7: 115:Core/Src/stm32f1xx_it.c **** /* USER CODE BEGIN BusFault_IRQn 0 */ 116:Core/Src/stm32f1xx_it.c **** 117:Core/Src/stm32f1xx_it.c **** /* USER CODE END BusFault_IRQn 0 */ 118:Core/Src/stm32f1xx_it.c **** while (1) 100 .loc 1 118 3 discriminator 1 view .LVU9 119:Core/Src/stm32f1xx_it.c **** { 120:Core/Src/stm32f1xx_it.c **** /* USER CODE BEGIN W1_BusFault_IRQn 0 */ 121:Core/Src/stm32f1xx_it.c **** /* USER CODE END W1_BusFault_IRQn 0 */ 122:Core/Src/stm32f1xx_it.c **** } 101 .loc 1 122 3 discriminator 1 view .LVU10 102 0000 FEE7 b .L7 103 .cfi_endproc 104 .LFE68: 106 .section .text.UsageFault_Handler,"ax",%progbits 107 .align 1 108 .global UsageFault_Handler 109 .syntax unified 110 .thumb 111 .thumb_func 112 .fpu softvfp 114 UsageFault_Handler: 115 .LFB69: ARM GAS /tmp/ccOMxQCE.s page 5 123:Core/Src/stm32f1xx_it.c **** } 124:Core/Src/stm32f1xx_it.c **** 125:Core/Src/stm32f1xx_it.c **** /** 126:Core/Src/stm32f1xx_it.c **** * @brief This function handles Undefined instruction or illegal state. 127:Core/Src/stm32f1xx_it.c **** */ 128:Core/Src/stm32f1xx_it.c **** void UsageFault_Handler(void) 129:Core/Src/stm32f1xx_it.c **** { 116 .loc 1 129 1 view -0 117 .cfi_startproc 118 @ Volatile: function does not return. 119 @ args = 0, pretend = 0, frame = 0 120 @ frame_needed = 0, uses_anonymous_args = 0 121 @ link register save eliminated. 122 .L9: 130:Core/Src/stm32f1xx_it.c **** /* USER CODE BEGIN UsageFault_IRQn 0 */ 131:Core/Src/stm32f1xx_it.c **** 132:Core/Src/stm32f1xx_it.c **** /* USER CODE END UsageFault_IRQn 0 */ 133:Core/Src/stm32f1xx_it.c **** while (1) 123 .loc 1 133 3 discriminator 1 view .LVU12 134:Core/Src/stm32f1xx_it.c **** { 135:Core/Src/stm32f1xx_it.c **** /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ 136:Core/Src/stm32f1xx_it.c **** /* USER CODE END W1_UsageFault_IRQn 0 */ 137:Core/Src/stm32f1xx_it.c **** } 124 .loc 1 137 3 discriminator 1 view .LVU13 125 0000 FEE7 b .L9 126 .cfi_endproc 127 .LFE69: 129 .section .text.SVC_Handler,"ax",%progbits 130 .align 1 131 .global SVC_Handler 132 .syntax unified 133 .thumb 134 .thumb_func 135 .fpu softvfp 137 SVC_Handler: 138 .LFB70: 138:Core/Src/stm32f1xx_it.c **** } 139:Core/Src/stm32f1xx_it.c **** 140:Core/Src/stm32f1xx_it.c **** /** 141:Core/Src/stm32f1xx_it.c **** * @brief This function handles System service call via SWI instruction. 142:Core/Src/stm32f1xx_it.c **** */ 143:Core/Src/stm32f1xx_it.c **** void SVC_Handler(void) 144:Core/Src/stm32f1xx_it.c **** { 139 .loc 1 144 1 view -0 140 .cfi_startproc 141 @ args = 0, pretend = 0, frame = 0 142 @ frame_needed = 0, uses_anonymous_args = 0 143 @ link register save eliminated. 145:Core/Src/stm32f1xx_it.c **** /* USER CODE BEGIN SVCall_IRQn 0 */ 146:Core/Src/stm32f1xx_it.c **** 147:Core/Src/stm32f1xx_it.c **** /* USER CODE END SVCall_IRQn 0 */ 148:Core/Src/stm32f1xx_it.c **** /* USER CODE BEGIN SVCall_IRQn 1 */ 149:Core/Src/stm32f1xx_it.c **** 150:Core/Src/stm32f1xx_it.c **** /* USER CODE END SVCall_IRQn 1 */ 151:Core/Src/stm32f1xx_it.c **** } 144 .loc 1 151 1 view .LVU15 145 0000 7047 bx lr ARM GAS /tmp/ccOMxQCE.s page 6 146 .cfi_endproc 147 .LFE70: 149 .section .text.DebugMon_Handler,"ax",%progbits 150 .align 1 151 .global DebugMon_Handler 152 .syntax unified 153 .thumb 154 .thumb_func 155 .fpu softvfp 157 DebugMon_Handler: 158 .LFB71: 152:Core/Src/stm32f1xx_it.c **** 153:Core/Src/stm32f1xx_it.c **** /** 154:Core/Src/stm32f1xx_it.c **** * @brief This function handles Debug monitor. 155:Core/Src/stm32f1xx_it.c **** */ 156:Core/Src/stm32f1xx_it.c **** void DebugMon_Handler(void) 157:Core/Src/stm32f1xx_it.c **** { 159 .loc 1 157 1 view -0 160 .cfi_startproc 161 @ args = 0, pretend = 0, frame = 0 162 @ frame_needed = 0, uses_anonymous_args = 0 163 @ link register save eliminated. 158:Core/Src/stm32f1xx_it.c **** /* USER CODE BEGIN DebugMonitor_IRQn 0 */ 159:Core/Src/stm32f1xx_it.c **** 160:Core/Src/stm32f1xx_it.c **** /* USER CODE END DebugMonitor_IRQn 0 */ 161:Core/Src/stm32f1xx_it.c **** /* USER CODE BEGIN DebugMonitor_IRQn 1 */ 162:Core/Src/stm32f1xx_it.c **** 163:Core/Src/stm32f1xx_it.c **** /* USER CODE END DebugMonitor_IRQn 1 */ 164:Core/Src/stm32f1xx_it.c **** } 164 .loc 1 164 1 view .LVU17 165 0000 7047 bx lr 166 .cfi_endproc 167 .LFE71: 169 .section .text.PendSV_Handler,"ax",%progbits 170 .align 1 171 .global PendSV_Handler 172 .syntax unified 173 .thumb 174 .thumb_func 175 .fpu softvfp 177 PendSV_Handler: 178 .LFB72: 165:Core/Src/stm32f1xx_it.c **** 166:Core/Src/stm32f1xx_it.c **** /** 167:Core/Src/stm32f1xx_it.c **** * @brief This function handles Pendable request for system service. 168:Core/Src/stm32f1xx_it.c **** */ 169:Core/Src/stm32f1xx_it.c **** void PendSV_Handler(void) 170:Core/Src/stm32f1xx_it.c **** { 179 .loc 1 170 1 view -0 180 .cfi_startproc 181 @ args = 0, pretend = 0, frame = 0 182 @ frame_needed = 0, uses_anonymous_args = 0 183 @ link register save eliminated. 171:Core/Src/stm32f1xx_it.c **** /* USER CODE BEGIN PendSV_IRQn 0 */ 172:Core/Src/stm32f1xx_it.c **** 173:Core/Src/stm32f1xx_it.c **** /* USER CODE END PendSV_IRQn 0 */ 174:Core/Src/stm32f1xx_it.c **** /* USER CODE BEGIN PendSV_IRQn 1 */ ARM GAS /tmp/ccOMxQCE.s page 7 175:Core/Src/stm32f1xx_it.c **** 176:Core/Src/stm32f1xx_it.c **** /* USER CODE END PendSV_IRQn 1 */ 177:Core/Src/stm32f1xx_it.c **** } 184 .loc 1 177 1 view .LVU19 185 0000 7047 bx lr 186 .cfi_endproc 187 .LFE72: 189 .section .text.SysTick_Handler,"ax",%progbits 190 .align 1 191 .global SysTick_Handler 192 .syntax unified 193 .thumb 194 .thumb_func 195 .fpu softvfp 197 SysTick_Handler: 198 .LFB73: 178:Core/Src/stm32f1xx_it.c **** 179:Core/Src/stm32f1xx_it.c **** /** 180:Core/Src/stm32f1xx_it.c **** * @brief This function handles System tick timer. 181:Core/Src/stm32f1xx_it.c **** */ 182:Core/Src/stm32f1xx_it.c **** void SysTick_Handler(void) 183:Core/Src/stm32f1xx_it.c **** { 199 .loc 1 183 1 view -0 200 .cfi_startproc 201 @ args = 0, pretend = 0, frame = 0 202 @ frame_needed = 0, uses_anonymous_args = 0 203 0000 08B5 push {r3, lr} 204 .LCFI0: 205 .cfi_def_cfa_offset 8 206 .cfi_offset 3, -8 207 .cfi_offset 14, -4 184:Core/Src/stm32f1xx_it.c **** /* USER CODE BEGIN SysTick_IRQn 0 */ 185:Core/Src/stm32f1xx_it.c **** 186:Core/Src/stm32f1xx_it.c **** /* USER CODE END SysTick_IRQn 0 */ 187:Core/Src/stm32f1xx_it.c **** HAL_IncTick(); 208 .loc 1 187 3 view .LVU21 209 0002 FFF7FEFF bl HAL_IncTick 210 .LVL0: 188:Core/Src/stm32f1xx_it.c **** /* USER CODE BEGIN SysTick_IRQn 1 */ 189:Core/Src/stm32f1xx_it.c **** 190:Core/Src/stm32f1xx_it.c **** /* USER CODE END SysTick_IRQn 1 */ 191:Core/Src/stm32f1xx_it.c **** } 211 .loc 1 191 1 is_stmt 0 view .LVU22 212 0006 08BD pop {r3, pc} 213 .cfi_endproc 214 .LFE73: 216 .text 217 .Letext0: 218 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" 219 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h" 220 .file 4 "Drivers/CMSIS/Include/core_cm3.h" 221 .file 5 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h" 222 .file 6 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h" ARM GAS /tmp/ccOMxQCE.s page 8 DEFINED SYMBOLS *ABS*:0000000000000000 stm32f1xx_it.c /tmp/ccOMxQCE.s:16 .text.NMI_Handler:0000000000000000 $t /tmp/ccOMxQCE.s:24 .text.NMI_Handler:0000000000000000 NMI_Handler /tmp/ccOMxQCE.s:38 .text.HardFault_Handler:0000000000000000 $t /tmp/ccOMxQCE.s:45 .text.HardFault_Handler:0000000000000000 HardFault_Handler /tmp/ccOMxQCE.s:61 .text.MemManage_Handler:0000000000000000 $t /tmp/ccOMxQCE.s:68 .text.MemManage_Handler:0000000000000000 MemManage_Handler /tmp/ccOMxQCE.s:84 .text.BusFault_Handler:0000000000000000 $t /tmp/ccOMxQCE.s:91 .text.BusFault_Handler:0000000000000000 BusFault_Handler /tmp/ccOMxQCE.s:107 .text.UsageFault_Handler:0000000000000000 $t /tmp/ccOMxQCE.s:114 .text.UsageFault_Handler:0000000000000000 UsageFault_Handler /tmp/ccOMxQCE.s:130 .text.SVC_Handler:0000000000000000 $t /tmp/ccOMxQCE.s:137 .text.SVC_Handler:0000000000000000 SVC_Handler /tmp/ccOMxQCE.s:150 .text.DebugMon_Handler:0000000000000000 $t /tmp/ccOMxQCE.s:157 .text.DebugMon_Handler:0000000000000000 DebugMon_Handler /tmp/ccOMxQCE.s:170 .text.PendSV_Handler:0000000000000000 $t /tmp/ccOMxQCE.s:177 .text.PendSV_Handler:0000000000000000 PendSV_Handler /tmp/ccOMxQCE.s:190 .text.SysTick_Handler:0000000000000000 $t /tmp/ccOMxQCE.s:197 .text.SysTick_Handler:0000000000000000 SysTick_Handler UNDEFINED SYMBOLS HAL_IncTick