ARM GAS /tmp/ccEGCTiT.s page 1 1 .cpu cortex-m3 2 .eabi_attribute 20, 1 3 .eabi_attribute 21, 1 4 .eabi_attribute 23, 3 5 .eabi_attribute 24, 1 6 .eabi_attribute 25, 1 7 .eabi_attribute 26, 1 8 .eabi_attribute 30, 1 9 .eabi_attribute 34, 1 10 .eabi_attribute 18, 4 11 .file "stm32f1xx_hal_msp.c" 12 .text 13 .Ltext0: 14 .cfi_sections .debug_frame 15 .section .text.HAL_MspInit,"ax",%progbits 16 .align 1 17 .global HAL_MspInit 18 .arch armv7-m 19 .syntax unified 20 .thumb 21 .thumb_func 22 .fpu softvfp 24 HAL_MspInit: 25 .LFB65: 26 .file 1 "Core/Src/stm32f1xx_hal_msp.c" 1:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN Header */ 2:Core/Src/stm32f1xx_hal_msp.c **** /** 3:Core/Src/stm32f1xx_hal_msp.c **** ****************************************************************************** 4:Core/Src/stm32f1xx_hal_msp.c **** * File Name : stm32f1xx_hal_msp.c 5:Core/Src/stm32f1xx_hal_msp.c **** * Description : This file provides code for the MSP Initialization 6:Core/Src/stm32f1xx_hal_msp.c **** * and de-Initialization codes. 7:Core/Src/stm32f1xx_hal_msp.c **** ****************************************************************************** 8:Core/Src/stm32f1xx_hal_msp.c **** * @attention 9:Core/Src/stm32f1xx_hal_msp.c **** * 10:Core/Src/stm32f1xx_hal_msp.c **** *

© Copyright (c) 2020 STMicroelectronics. 11:Core/Src/stm32f1xx_hal_msp.c **** * All rights reserved.

12:Core/Src/stm32f1xx_hal_msp.c **** * 13:Core/Src/stm32f1xx_hal_msp.c **** * This software component is licensed by ST under BSD 3-Clause license, 14:Core/Src/stm32f1xx_hal_msp.c **** * the "License"; You may not use this file except in compliance with the 15:Core/Src/stm32f1xx_hal_msp.c **** * License. You may obtain a copy of the License at: 16:Core/Src/stm32f1xx_hal_msp.c **** * opensource.org/licenses/BSD-3-Clause 17:Core/Src/stm32f1xx_hal_msp.c **** * 18:Core/Src/stm32f1xx_hal_msp.c **** ****************************************************************************** 19:Core/Src/stm32f1xx_hal_msp.c **** */ 20:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END Header */ 21:Core/Src/stm32f1xx_hal_msp.c **** 22:Core/Src/stm32f1xx_hal_msp.c **** /* Includes ------------------------------------------------------------------*/ 23:Core/Src/stm32f1xx_hal_msp.c **** #include "main.h" 24:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN Includes */ 25:Core/Src/stm32f1xx_hal_msp.c **** 26:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END Includes */ 27:Core/Src/stm32f1xx_hal_msp.c **** 28:Core/Src/stm32f1xx_hal_msp.c **** /* Private typedef -----------------------------------------------------------*/ 29:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN TD */ 30:Core/Src/stm32f1xx_hal_msp.c **** 31:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END TD */ 32:Core/Src/stm32f1xx_hal_msp.c **** ARM GAS /tmp/ccEGCTiT.s page 2 33:Core/Src/stm32f1xx_hal_msp.c **** /* Private define ------------------------------------------------------------*/ 34:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN Define */ 35:Core/Src/stm32f1xx_hal_msp.c **** 36:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END Define */ 37:Core/Src/stm32f1xx_hal_msp.c **** 38:Core/Src/stm32f1xx_hal_msp.c **** /* Private macro -------------------------------------------------------------*/ 39:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN Macro */ 40:Core/Src/stm32f1xx_hal_msp.c **** 41:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END Macro */ 42:Core/Src/stm32f1xx_hal_msp.c **** 43:Core/Src/stm32f1xx_hal_msp.c **** /* Private variables ---------------------------------------------------------*/ 44:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN PV */ 45:Core/Src/stm32f1xx_hal_msp.c **** 46:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END PV */ 47:Core/Src/stm32f1xx_hal_msp.c **** 48:Core/Src/stm32f1xx_hal_msp.c **** /* Private function prototypes -----------------------------------------------*/ 49:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN PFP */ 50:Core/Src/stm32f1xx_hal_msp.c **** 51:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END PFP */ 52:Core/Src/stm32f1xx_hal_msp.c **** 53:Core/Src/stm32f1xx_hal_msp.c **** /* External functions --------------------------------------------------------*/ 54:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN ExternalFunctions */ 55:Core/Src/stm32f1xx_hal_msp.c **** 56:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END ExternalFunctions */ 57:Core/Src/stm32f1xx_hal_msp.c **** 58:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN 0 */ 59:Core/Src/stm32f1xx_hal_msp.c **** 60:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END 0 */ 61:Core/Src/stm32f1xx_hal_msp.c **** /** 62:Core/Src/stm32f1xx_hal_msp.c **** * Initializes the Global MSP. 63:Core/Src/stm32f1xx_hal_msp.c **** */ 64:Core/Src/stm32f1xx_hal_msp.c **** void HAL_MspInit(void) 65:Core/Src/stm32f1xx_hal_msp.c **** { 27 .loc 1 65 1 view -0 28 .cfi_startproc 29 @ args = 0, pretend = 0, frame = 8 30 @ frame_needed = 0, uses_anonymous_args = 0 31 @ link register save eliminated. 32 0000 82B0 sub sp, sp, #8 33 .LCFI0: 34 .cfi_def_cfa_offset 8 66:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN MspInit 0 */ 67:Core/Src/stm32f1xx_hal_msp.c **** 68:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END MspInit 0 */ 69:Core/Src/stm32f1xx_hal_msp.c **** 70:Core/Src/stm32f1xx_hal_msp.c **** __HAL_RCC_AFIO_CLK_ENABLE(); 35 .loc 1 70 3 view .LVU1 36 .LBB2: 37 .loc 1 70 3 view .LVU2 38 .loc 1 70 3 view .LVU3 39 0002 0E4B ldr r3, .L3 40 0004 9A69 ldr r2, [r3, #24] 41 0006 42F00102 orr r2, r2, #1 42 000a 9A61 str r2, [r3, #24] 43 .loc 1 70 3 view .LVU4 44 000c 9A69 ldr r2, [r3, #24] 45 000e 02F00102 and r2, r2, #1 ARM GAS /tmp/ccEGCTiT.s page 3 46 0012 0092 str r2, [sp] 47 .loc 1 70 3 view .LVU5 48 0014 009A ldr r2, [sp] 49 .LBE2: 71:Core/Src/stm32f1xx_hal_msp.c **** __HAL_RCC_PWR_CLK_ENABLE(); 50 .loc 1 71 3 view .LVU6 51 .LBB3: 52 .loc 1 71 3 view .LVU7 53 .loc 1 71 3 view .LVU8 54 0016 DA69 ldr r2, [r3, #28] 55 0018 42F08052 orr r2, r2, #268435456 56 001c DA61 str r2, [r3, #28] 57 .loc 1 71 3 view .LVU9 58 001e DB69 ldr r3, [r3, #28] 59 0020 03F08053 and r3, r3, #268435456 60 0024 0193 str r3, [sp, #4] 61 .loc 1 71 3 view .LVU10 62 0026 019B ldr r3, [sp, #4] 63 .LBE3: 72:Core/Src/stm32f1xx_hal_msp.c **** 73:Core/Src/stm32f1xx_hal_msp.c **** /* System interrupt init*/ 74:Core/Src/stm32f1xx_hal_msp.c **** 75:Core/Src/stm32f1xx_hal_msp.c **** /** DISABLE: JTAG-DP Disabled and SW-DP Disabled 76:Core/Src/stm32f1xx_hal_msp.c **** */ 77:Core/Src/stm32f1xx_hal_msp.c **** __HAL_AFIO_REMAP_SWJ_DISABLE(); 64 .loc 1 77 3 view .LVU11 65 .LBB4: 66 .loc 1 77 3 view .LVU12 67 0028 054A ldr r2, .L3+4 68 002a 5368 ldr r3, [r2, #4] 69 .LVL0: 70 .loc 1 77 3 view .LVU13 71 002c 23F0E063 bic r3, r3, #117440512 72 .LVL1: 73 .loc 1 77 3 view .LVU14 74 0030 43F08063 orr r3, r3, #67108864 75 .LVL2: 76 .loc 1 77 3 view .LVU15 77 0034 5360 str r3, [r2, #4] 78 .LBE4: 78:Core/Src/stm32f1xx_hal_msp.c **** 79:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN MspInit 1 */ 80:Core/Src/stm32f1xx_hal_msp.c **** 81:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END MspInit 1 */ 82:Core/Src/stm32f1xx_hal_msp.c **** } 79 .loc 1 82 1 is_stmt 0 view .LVU16 80 0036 02B0 add sp, sp, #8 81 .LCFI1: 82 .cfi_def_cfa_offset 0 83 @ sp needed 84 0038 7047 bx lr 85 .L4: 86 003a 00BF .align 2 87 .L3: 88 003c 00100240 .word 1073876992 89 0040 00000140 .word 1073807360 90 .cfi_endproc ARM GAS /tmp/ccEGCTiT.s page 4 91 .LFE65: 93 .section .text.HAL_CAN_MspInit,"ax",%progbits 94 .align 1 95 .global HAL_CAN_MspInit 96 .syntax unified 97 .thumb 98 .thumb_func 99 .fpu softvfp 101 HAL_CAN_MspInit: 102 .LVL3: 103 .LFB66: 83:Core/Src/stm32f1xx_hal_msp.c **** 84:Core/Src/stm32f1xx_hal_msp.c **** /** 85:Core/Src/stm32f1xx_hal_msp.c **** * @brief CAN MSP Initialization 86:Core/Src/stm32f1xx_hal_msp.c **** * This function configures the hardware resources used in this example 87:Core/Src/stm32f1xx_hal_msp.c **** * @param hcan: CAN handle pointer 88:Core/Src/stm32f1xx_hal_msp.c **** * @retval None 89:Core/Src/stm32f1xx_hal_msp.c **** */ 90:Core/Src/stm32f1xx_hal_msp.c **** void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan) 91:Core/Src/stm32f1xx_hal_msp.c **** { 104 .loc 1 91 1 is_stmt 1 view -0 105 .cfi_startproc 106 @ args = 0, pretend = 0, frame = 24 107 @ frame_needed = 0, uses_anonymous_args = 0 108 .loc 1 91 1 is_stmt 0 view .LVU18 109 0000 10B5 push {r4, lr} 110 .LCFI2: 111 .cfi_def_cfa_offset 8 112 .cfi_offset 4, -8 113 .cfi_offset 14, -4 114 0002 86B0 sub sp, sp, #24 115 .LCFI3: 116 .cfi_def_cfa_offset 32 92:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitTypeDef GPIO_InitStruct = {0}; 117 .loc 1 92 3 is_stmt 1 view .LVU19 118 .loc 1 92 20 is_stmt 0 view .LVU20 119 0004 0023 movs r3, #0 120 0006 0293 str r3, [sp, #8] 121 0008 0393 str r3, [sp, #12] 122 000a 0493 str r3, [sp, #16] 123 000c 0593 str r3, [sp, #20] 93:Core/Src/stm32f1xx_hal_msp.c **** if(hcan->Instance==CAN1) 124 .loc 1 93 3 is_stmt 1 view .LVU21 125 .loc 1 93 10 is_stmt 0 view .LVU22 126 000e 0268 ldr r2, [r0] 127 .loc 1 93 5 view .LVU23 128 0010 1A4B ldr r3, .L9 129 0012 9A42 cmp r2, r3 130 0014 01D0 beq .L8 131 .LVL4: 132 .L5: 94:Core/Src/stm32f1xx_hal_msp.c **** { 95:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN CAN1_MspInit 0 */ 96:Core/Src/stm32f1xx_hal_msp.c **** 97:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END CAN1_MspInit 0 */ 98:Core/Src/stm32f1xx_hal_msp.c **** /* Peripheral clock enable */ 99:Core/Src/stm32f1xx_hal_msp.c **** __HAL_RCC_CAN1_CLK_ENABLE(); ARM GAS /tmp/ccEGCTiT.s page 5 100:Core/Src/stm32f1xx_hal_msp.c **** 101:Core/Src/stm32f1xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE(); 102:Core/Src/stm32f1xx_hal_msp.c **** /**CAN GPIO Configuration 103:Core/Src/stm32f1xx_hal_msp.c **** PB8 ------> CAN_RX 104:Core/Src/stm32f1xx_hal_msp.c **** PB9 ------> CAN_TX 105:Core/Src/stm32f1xx_hal_msp.c **** */ 106:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Pin = GPIO_PIN_8; 107:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 108:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 109:Core/Src/stm32f1xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 110:Core/Src/stm32f1xx_hal_msp.c **** 111:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Pin = GPIO_PIN_9; 112:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 113:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 114:Core/Src/stm32f1xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 115:Core/Src/stm32f1xx_hal_msp.c **** 116:Core/Src/stm32f1xx_hal_msp.c **** __HAL_AFIO_REMAP_CAN1_2(); 117:Core/Src/stm32f1xx_hal_msp.c **** 118:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN CAN1_MspInit 1 */ 119:Core/Src/stm32f1xx_hal_msp.c **** 120:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END CAN1_MspInit 1 */ 121:Core/Src/stm32f1xx_hal_msp.c **** } 122:Core/Src/stm32f1xx_hal_msp.c **** 123:Core/Src/stm32f1xx_hal_msp.c **** } 133 .loc 1 123 1 view .LVU24 134 0016 06B0 add sp, sp, #24 135 .LCFI4: 136 .cfi_remember_state 137 .cfi_def_cfa_offset 8 138 @ sp needed 139 0018 10BD pop {r4, pc} 140 .LVL5: 141 .L8: 142 .LCFI5: 143 .cfi_restore_state 99:Core/Src/stm32f1xx_hal_msp.c **** 144 .loc 1 99 5 is_stmt 1 view .LVU25 145 .LBB5: 99:Core/Src/stm32f1xx_hal_msp.c **** 146 .loc 1 99 5 view .LVU26 99:Core/Src/stm32f1xx_hal_msp.c **** 147 .loc 1 99 5 view .LVU27 148 001a 03F5D633 add r3, r3, #109568 149 001e DA69 ldr r2, [r3, #28] 150 0020 42F00072 orr r2, r2, #33554432 151 0024 DA61 str r2, [r3, #28] 99:Core/Src/stm32f1xx_hal_msp.c **** 152 .loc 1 99 5 view .LVU28 153 0026 DA69 ldr r2, [r3, #28] 154 0028 02F00072 and r2, r2, #33554432 155 002c 0092 str r2, [sp] 99:Core/Src/stm32f1xx_hal_msp.c **** 156 .loc 1 99 5 view .LVU29 157 002e 009A ldr r2, [sp] 158 .LBE5: 101:Core/Src/stm32f1xx_hal_msp.c **** /**CAN GPIO Configuration 159 .loc 1 101 5 view .LVU30 ARM GAS /tmp/ccEGCTiT.s page 6 160 .LBB6: 101:Core/Src/stm32f1xx_hal_msp.c **** /**CAN GPIO Configuration 161 .loc 1 101 5 view .LVU31 101:Core/Src/stm32f1xx_hal_msp.c **** /**CAN GPIO Configuration 162 .loc 1 101 5 view .LVU32 163 0030 9A69 ldr r2, [r3, #24] 164 0032 42F00802 orr r2, r2, #8 165 0036 9A61 str r2, [r3, #24] 101:Core/Src/stm32f1xx_hal_msp.c **** /**CAN GPIO Configuration 166 .loc 1 101 5 view .LVU33 167 0038 9B69 ldr r3, [r3, #24] 168 003a 03F00803 and r3, r3, #8 169 003e 0193 str r3, [sp, #4] 101:Core/Src/stm32f1xx_hal_msp.c **** /**CAN GPIO Configuration 170 .loc 1 101 5 view .LVU34 171 0040 019B ldr r3, [sp, #4] 172 .LBE6: 106:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 173 .loc 1 106 5 view .LVU35 106:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 174 .loc 1 106 25 is_stmt 0 view .LVU36 175 0042 4FF48073 mov r3, #256 176 0046 0293 str r3, [sp, #8] 107:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 177 .loc 1 107 5 is_stmt 1 view .LVU37 108:Core/Src/stm32f1xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 178 .loc 1 108 5 view .LVU38 109:Core/Src/stm32f1xx_hal_msp.c **** 179 .loc 1 109 5 view .LVU39 180 0048 0D4C ldr r4, .L9+4 181 004a 02A9 add r1, sp, #8 182 004c 2046 mov r0, r4 183 .LVL6: 109:Core/Src/stm32f1xx_hal_msp.c **** 184 .loc 1 109 5 is_stmt 0 view .LVU40 185 004e FFF7FEFF bl HAL_GPIO_Init 186 .LVL7: 111:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 187 .loc 1 111 5 is_stmt 1 view .LVU41 111:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 188 .loc 1 111 25 is_stmt 0 view .LVU42 189 0052 4FF40073 mov r3, #512 190 0056 0293 str r3, [sp, #8] 112:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 191 .loc 1 112 5 is_stmt 1 view .LVU43 112:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 192 .loc 1 112 26 is_stmt 0 view .LVU44 193 0058 0223 movs r3, #2 194 005a 0393 str r3, [sp, #12] 113:Core/Src/stm32f1xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 195 .loc 1 113 5 is_stmt 1 view .LVU45 113:Core/Src/stm32f1xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 196 .loc 1 113 27 is_stmt 0 view .LVU46 197 005c 0323 movs r3, #3 198 005e 0593 str r3, [sp, #20] 114:Core/Src/stm32f1xx_hal_msp.c **** 199 .loc 1 114 5 is_stmt 1 view .LVU47 ARM GAS /tmp/ccEGCTiT.s page 7 200 0060 02A9 add r1, sp, #8 201 0062 2046 mov r0, r4 202 0064 FFF7FEFF bl HAL_GPIO_Init 203 .LVL8: 116:Core/Src/stm32f1xx_hal_msp.c **** 204 .loc 1 116 5 view .LVU48 205 .LBB7: 116:Core/Src/stm32f1xx_hal_msp.c **** 206 .loc 1 116 5 view .LVU49 207 0068 064A ldr r2, .L9+8 208 006a 5368 ldr r3, [r2, #4] 209 .LVL9: 116:Core/Src/stm32f1xx_hal_msp.c **** 210 .loc 1 116 5 view .LVU50 211 006c 23F4C043 bic r3, r3, #24576 212 .LVL10: 116:Core/Src/stm32f1xx_hal_msp.c **** 213 .loc 1 116 5 view .LVU51 116:Core/Src/stm32f1xx_hal_msp.c **** 214 .loc 1 116 5 view .LVU52 215 0070 43F0E063 orr r3, r3, #117440512 216 .LVL11: 116:Core/Src/stm32f1xx_hal_msp.c **** 217 .loc 1 116 5 is_stmt 0 view .LVU53 218 0074 43F48043 orr r3, r3, #16384 219 .LVL12: 116:Core/Src/stm32f1xx_hal_msp.c **** 220 .loc 1 116 5 is_stmt 1 view .LVU54 221 0078 5360 str r3, [r2, #4] 222 .LBE7: 223 .loc 1 123 1 is_stmt 0 view .LVU55 224 007a CCE7 b .L5 225 .L10: 226 .align 2 227 .L9: 228 007c 00640040 .word 1073767424 229 0080 000C0140 .word 1073810432 230 0084 00000140 .word 1073807360 231 .cfi_endproc 232 .LFE66: 234 .section .text.HAL_CAN_MspDeInit,"ax",%progbits 235 .align 1 236 .global HAL_CAN_MspDeInit 237 .syntax unified 238 .thumb 239 .thumb_func 240 .fpu softvfp 242 HAL_CAN_MspDeInit: 243 .LVL13: 244 .LFB67: 124:Core/Src/stm32f1xx_hal_msp.c **** 125:Core/Src/stm32f1xx_hal_msp.c **** /** 126:Core/Src/stm32f1xx_hal_msp.c **** * @brief CAN MSP De-Initialization 127:Core/Src/stm32f1xx_hal_msp.c **** * This function freeze the hardware resources used in this example 128:Core/Src/stm32f1xx_hal_msp.c **** * @param hcan: CAN handle pointer 129:Core/Src/stm32f1xx_hal_msp.c **** * @retval None 130:Core/Src/stm32f1xx_hal_msp.c **** */ ARM GAS /tmp/ccEGCTiT.s page 8 131:Core/Src/stm32f1xx_hal_msp.c **** void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan) 132:Core/Src/stm32f1xx_hal_msp.c **** { 245 .loc 1 132 1 is_stmt 1 view -0 246 .cfi_startproc 247 @ args = 0, pretend = 0, frame = 0 248 @ frame_needed = 0, uses_anonymous_args = 0 249 .loc 1 132 1 is_stmt 0 view .LVU57 250 0000 08B5 push {r3, lr} 251 .LCFI6: 252 .cfi_def_cfa_offset 8 253 .cfi_offset 3, -8 254 .cfi_offset 14, -4 133:Core/Src/stm32f1xx_hal_msp.c **** if(hcan->Instance==CAN1) 255 .loc 1 133 3 is_stmt 1 view .LVU58 256 .loc 1 133 10 is_stmt 0 view .LVU59 257 0002 0268 ldr r2, [r0] 258 .loc 1 133 5 view .LVU60 259 0004 074B ldr r3, .L15 260 0006 9A42 cmp r2, r3 261 0008 00D0 beq .L14 262 .LVL14: 263 .L11: 134:Core/Src/stm32f1xx_hal_msp.c **** { 135:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN CAN1_MspDeInit 0 */ 136:Core/Src/stm32f1xx_hal_msp.c **** 137:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END CAN1_MspDeInit 0 */ 138:Core/Src/stm32f1xx_hal_msp.c **** /* Peripheral clock disable */ 139:Core/Src/stm32f1xx_hal_msp.c **** __HAL_RCC_CAN1_CLK_DISABLE(); 140:Core/Src/stm32f1xx_hal_msp.c **** 141:Core/Src/stm32f1xx_hal_msp.c **** /**CAN GPIO Configuration 142:Core/Src/stm32f1xx_hal_msp.c **** PB8 ------> CAN_RX 143:Core/Src/stm32f1xx_hal_msp.c **** PB9 ------> CAN_TX 144:Core/Src/stm32f1xx_hal_msp.c **** */ 145:Core/Src/stm32f1xx_hal_msp.c **** HAL_GPIO_DeInit(GPIOB, GPIO_PIN_8|GPIO_PIN_9); 146:Core/Src/stm32f1xx_hal_msp.c **** 147:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN CAN1_MspDeInit 1 */ 148:Core/Src/stm32f1xx_hal_msp.c **** 149:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END CAN1_MspDeInit 1 */ 150:Core/Src/stm32f1xx_hal_msp.c **** } 151:Core/Src/stm32f1xx_hal_msp.c **** 152:Core/Src/stm32f1xx_hal_msp.c **** } 264 .loc 1 152 1 view .LVU61 265 000a 08BD pop {r3, pc} 266 .LVL15: 267 .L14: 139:Core/Src/stm32f1xx_hal_msp.c **** 268 .loc 1 139 5 is_stmt 1 view .LVU62 269 000c 064A ldr r2, .L15+4 270 000e D369 ldr r3, [r2, #28] 271 0010 23F00073 bic r3, r3, #33554432 272 0014 D361 str r3, [r2, #28] 145:Core/Src/stm32f1xx_hal_msp.c **** 273 .loc 1 145 5 view .LVU63 274 0016 4FF44071 mov r1, #768 275 001a 0448 ldr r0, .L15+8 276 .LVL16: 145:Core/Src/stm32f1xx_hal_msp.c **** ARM GAS /tmp/ccEGCTiT.s page 9 277 .loc 1 145 5 is_stmt 0 view .LVU64 278 001c FFF7FEFF bl HAL_GPIO_DeInit 279 .LVL17: 280 .loc 1 152 1 view .LVU65 281 0020 F3E7 b .L11 282 .L16: 283 0022 00BF .align 2 284 .L15: 285 0024 00640040 .word 1073767424 286 0028 00100240 .word 1073876992 287 002c 000C0140 .word 1073810432 288 .cfi_endproc 289 .LFE67: 291 .text 292 .Letext0: 293 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" 294 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h" 295 .file 4 "Drivers/CMSIS/Include/core_cm3.h" 296 .file 5 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h" 297 .file 6 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h" 298 .file 7 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h" 299 .file 8 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h" 300 .file 9 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h" 301 .file 10 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h" ARM GAS /tmp/ccEGCTiT.s page 10 DEFINED SYMBOLS *ABS*:0000000000000000 stm32f1xx_hal_msp.c /tmp/ccEGCTiT.s:16 .text.HAL_MspInit:0000000000000000 $t /tmp/ccEGCTiT.s:24 .text.HAL_MspInit:0000000000000000 HAL_MspInit /tmp/ccEGCTiT.s:88 .text.HAL_MspInit:000000000000003c $d /tmp/ccEGCTiT.s:94 .text.HAL_CAN_MspInit:0000000000000000 $t /tmp/ccEGCTiT.s:101 .text.HAL_CAN_MspInit:0000000000000000 HAL_CAN_MspInit /tmp/ccEGCTiT.s:228 .text.HAL_CAN_MspInit:000000000000007c $d /tmp/ccEGCTiT.s:235 .text.HAL_CAN_MspDeInit:0000000000000000 $t /tmp/ccEGCTiT.s:242 .text.HAL_CAN_MspDeInit:0000000000000000 HAL_CAN_MspDeInit /tmp/ccEGCTiT.s:285 .text.HAL_CAN_MspDeInit:0000000000000024 $d UNDEFINED SYMBOLS HAL_GPIO_Init HAL_GPIO_DeInit