2546 lines
165 KiB
Plaintext
2546 lines
165 KiB
Plaintext
ARM GAS /tmp/cc2owkii.s page 1
|
||
|
||
|
||
1 .cpu cortex-m3
|
||
2 .eabi_attribute 20, 1
|
||
3 .eabi_attribute 21, 1
|
||
4 .eabi_attribute 23, 3
|
||
5 .eabi_attribute 24, 1
|
||
6 .eabi_attribute 25, 1
|
||
7 .eabi_attribute 26, 1
|
||
8 .eabi_attribute 30, 1
|
||
9 .eabi_attribute 34, 1
|
||
10 .eabi_attribute 18, 4
|
||
11 .file "stm32f1xx_hal_pwr.c"
|
||
12 .text
|
||
13 .Ltext0:
|
||
14 .cfi_sections .debug_frame
|
||
15 .section .text.PWR_OverloadWfe,"ax",%progbits
|
||
16 .align 1
|
||
17 .arch armv7-m
|
||
18 .syntax unified
|
||
19 .thumb
|
||
20 .thumb_func
|
||
21 .fpu softvfp
|
||
23 PWR_OverloadWfe:
|
||
24 .LFB65:
|
||
25 .file 1 "Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c"
|
||
1:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /**
|
||
2:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** ******************************************************************************
|
||
3:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @file stm32f1xx_hal_pwr.c
|
||
4:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @author MCD Application Team
|
||
5:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @brief PWR HAL module driver.
|
||
6:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** *
|
||
7:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * This file provides firmware functions to manage the following
|
||
8:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * functionalities of the Power Controller (PWR) peripheral:
|
||
9:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * + Initialization/de-initialization functions
|
||
10:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * + Peripheral Control functions
|
||
11:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** *
|
||
12:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** ******************************************************************************
|
||
13:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @attention
|
||
14:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** *
|
||
15:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||
16:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * All rights reserved.</center></h2>
|
||
17:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** *
|
||
18:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * This software component is licensed by ST under BSD 3-Clause license,
|
||
19:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * the "License"; You may not use this file except in compliance with the
|
||
20:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * License. You may obtain a copy of the License at:
|
||
21:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * opensource.org/licenses/BSD-3-Clause
|
||
22:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** *
|
||
23:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** ******************************************************************************
|
||
24:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */
|
||
25:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
26:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Includes ------------------------------------------------------------------*/
|
||
27:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** #include "stm32f1xx_hal.h"
|
||
28:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
29:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /** @addtogroup STM32F1xx_HAL_Driver
|
||
30:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @{
|
||
31:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */
|
||
32:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
33:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /** @defgroup PWR PWR
|
||
ARM GAS /tmp/cc2owkii.s page 2
|
||
|
||
|
||
34:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @brief PWR HAL module driver
|
||
35:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @{
|
||
36:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */
|
||
37:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
38:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** #ifdef HAL_PWR_MODULE_ENABLED
|
||
39:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
40:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Private typedef -----------------------------------------------------------*/
|
||
41:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Private define ------------------------------------------------------------*/
|
||
42:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
43:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /** @defgroup PWR_Private_Constants PWR Private Constants
|
||
44:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @{
|
||
45:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */
|
||
46:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
47:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
|
||
48:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @{
|
||
49:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */
|
||
50:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** #define PVD_MODE_IT 0x00010000U
|
||
51:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** #define PVD_MODE_EVT 0x00020000U
|
||
52:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** #define PVD_RISING_EDGE 0x00000001U
|
||
53:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** #define PVD_FALLING_EDGE 0x00000002U
|
||
54:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /**
|
||
55:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @}
|
||
56:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */
|
||
57:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
58:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
59:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /** @defgroup PWR_register_alias_address PWR Register alias address
|
||
60:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @{
|
||
61:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */
|
||
62:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* ------------- PWR registers bit address in the alias region ---------------*/
|
||
63:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** #define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
|
||
64:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** #define PWR_CR_OFFSET 0x00U
|
||
65:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** #define PWR_CSR_OFFSET 0x04U
|
||
66:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** #define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET)
|
||
67:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** #define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET)
|
||
68:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /**
|
||
69:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @}
|
||
70:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */
|
||
71:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
72:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /** @defgroup PWR_CR_register_alias PWR CR Register alias address
|
||
73:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @{
|
||
74:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */
|
||
75:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* --- CR Register ---*/
|
||
76:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Alias word address of LPSDSR bit */
|
||
77:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** #define LPSDSR_BIT_NUMBER PWR_CR_LPDS_Pos
|
||
78:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** #define CR_LPSDSR_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (LPSDSR_BI
|
||
79:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
80:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Alias word address of DBP bit */
|
||
81:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** #define DBP_BIT_NUMBER PWR_CR_DBP_Pos
|
||
82:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** #define CR_DBP_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_N
|
||
83:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
84:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Alias word address of PVDE bit */
|
||
85:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** #define PVDE_BIT_NUMBER PWR_CR_PVDE_Pos
|
||
86:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** #define CR_PVDE_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_
|
||
87:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
88:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /**
|
||
89:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @}
|
||
90:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */
|
||
ARM GAS /tmp/cc2owkii.s page 3
|
||
|
||
|
||
91:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
92:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /** @defgroup PWR_CSR_register_alias PWR CSR Register alias address
|
||
93:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @{
|
||
94:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */
|
||
95:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
96:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* --- CSR Register ---*/
|
||
97:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Alias word address of EWUP1 bit */
|
||
98:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** #define CSR_EWUP_BB(VAL) ((uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (POSITION
|
||
99:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /**
|
||
100:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @}
|
||
101:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */
|
||
102:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
103:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /**
|
||
104:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @}
|
||
105:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */
|
||
106:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
107:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Private variables ---------------------------------------------------------*/
|
||
108:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Private function prototypes -----------------------------------------------*/
|
||
109:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /** @defgroup PWR_Private_Functions PWR Private Functions
|
||
110:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * brief WFE cortex command overloaded for HAL_PWR_EnterSTOPMode usage only (see Workaround secti
|
||
111:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @{
|
||
112:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */
|
||
113:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** static void PWR_OverloadWfe(void);
|
||
114:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
115:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Private functions ---------------------------------------------------------*/
|
||
116:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** __NOINLINE
|
||
117:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** static void PWR_OverloadWfe(void)
|
||
118:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** {
|
||
26 .loc 1 118 1 view -0
|
||
27 .cfi_startproc
|
||
28 @ args = 0, pretend = 0, frame = 0
|
||
29 @ frame_needed = 0, uses_anonymous_args = 0
|
||
30 @ link register save eliminated.
|
||
119:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** __asm volatile( "wfe" );
|
||
31 .loc 1 119 3 view .LVU1
|
||
32 .syntax unified
|
||
33 @ 119 "Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c" 1
|
||
34 0000 20BF wfe
|
||
35 @ 0 "" 2
|
||
120:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** __asm volatile( "nop" );
|
||
36 .loc 1 120 3 view .LVU2
|
||
37 @ 120 "Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c" 1
|
||
38 0002 00BF nop
|
||
39 @ 0 "" 2
|
||
121:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** }
|
||
40 .loc 1 121 1 is_stmt 0 view .LVU3
|
||
41 .thumb
|
||
42 .syntax unified
|
||
43 0004 7047 bx lr
|
||
44 .cfi_endproc
|
||
45 .LFE65:
|
||
47 .section .text.HAL_PWR_DeInit,"ax",%progbits
|
||
48 .align 1
|
||
49 .global HAL_PWR_DeInit
|
||
50 .syntax unified
|
||
51 .thumb
|
||
52 .thumb_func
|
||
ARM GAS /tmp/cc2owkii.s page 4
|
||
|
||
|
||
53 .fpu softvfp
|
||
55 HAL_PWR_DeInit:
|
||
56 .LFB66:
|
||
122:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
123:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /**
|
||
124:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @}
|
||
125:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */
|
||
126:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
127:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
128:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions PWR Exported Functions
|
||
129:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @{
|
||
130:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */
|
||
131:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
132:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
|
||
133:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @brief Initialization and de-initialization functions
|
||
134:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** *
|
||
135:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** @verbatim
|
||
136:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** ===============================================================================
|
||
137:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** ##### Initialization and de-initialization functions #####
|
||
138:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** ===============================================================================
|
||
139:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** [..]
|
||
140:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** After reset, the backup domain (RTC registers, RTC backup data
|
||
141:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** registers) is protected against possible unwanted
|
||
142:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** write accesses.
|
||
143:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** To enable access to the RTC Domain and RTC registers, proceed as follows:
|
||
144:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (+) Enable the Power Controller (PWR) APB1 interface clock using the
|
||
145:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** __HAL_RCC_PWR_CLK_ENABLE() macro.
|
||
146:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
|
||
147:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
148:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** @endverbatim
|
||
149:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @{
|
||
150:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */
|
||
151:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
152:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /**
|
||
153:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @brief Deinitializes the PWR peripheral registers to their default reset values.
|
||
154:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @retval None
|
||
155:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */
|
||
156:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** void HAL_PWR_DeInit(void)
|
||
157:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** {
|
||
57 .loc 1 157 1 is_stmt 1 view -0
|
||
58 .cfi_startproc
|
||
59 @ args = 0, pretend = 0, frame = 0
|
||
60 @ frame_needed = 0, uses_anonymous_args = 0
|
||
61 @ link register save eliminated.
|
||
158:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** __HAL_RCC_PWR_FORCE_RESET();
|
||
62 .loc 1 158 3 view .LVU5
|
||
63 0000 044B ldr r3, .L3
|
||
64 0002 1A69 ldr r2, [r3, #16]
|
||
65 0004 42F08052 orr r2, r2, #268435456
|
||
66 0008 1A61 str r2, [r3, #16]
|
||
159:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** __HAL_RCC_PWR_RELEASE_RESET();
|
||
67 .loc 1 159 3 view .LVU6
|
||
68 000a 1A69 ldr r2, [r3, #16]
|
||
69 000c 22F08052 bic r2, r2, #268435456
|
||
70 0010 1A61 str r2, [r3, #16]
|
||
160:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** }
|
||
71 .loc 1 160 1 is_stmt 0 view .LVU7
|
||
ARM GAS /tmp/cc2owkii.s page 5
|
||
|
||
|
||
72 0012 7047 bx lr
|
||
73 .L4:
|
||
74 .align 2
|
||
75 .L3:
|
||
76 0014 00100240 .word 1073876992
|
||
77 .cfi_endproc
|
||
78 .LFE66:
|
||
80 .section .text.HAL_PWR_EnableBkUpAccess,"ax",%progbits
|
||
81 .align 1
|
||
82 .global HAL_PWR_EnableBkUpAccess
|
||
83 .syntax unified
|
||
84 .thumb
|
||
85 .thumb_func
|
||
86 .fpu softvfp
|
||
88 HAL_PWR_EnableBkUpAccess:
|
||
89 .LFB67:
|
||
161:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
162:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /**
|
||
163:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @brief Enables access to the backup domain (RTC registers, RTC
|
||
164:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * backup data registers ).
|
||
165:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @note If the HSE divided by 128 is used as the RTC clock, the
|
||
166:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * Backup Domain Access should be kept enabled.
|
||
167:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @retval None
|
||
168:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */
|
||
169:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** void HAL_PWR_EnableBkUpAccess(void)
|
||
170:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** {
|
||
90 .loc 1 170 1 is_stmt 1 view -0
|
||
91 .cfi_startproc
|
||
92 @ args = 0, pretend = 0, frame = 0
|
||
93 @ frame_needed = 0, uses_anonymous_args = 0
|
||
94 @ link register save eliminated.
|
||
171:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Enable access to RTC and backup registers */
|
||
172:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE;
|
||
95 .loc 1 172 3 view .LVU9
|
||
96 .loc 1 172 32 is_stmt 0 view .LVU10
|
||
97 0000 014B ldr r3, .L6
|
||
98 0002 0122 movs r2, #1
|
||
99 0004 1A60 str r2, [r3]
|
||
173:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** }
|
||
100 .loc 1 173 1 view .LVU11
|
||
101 0006 7047 bx lr
|
||
102 .L7:
|
||
103 .align 2
|
||
104 .L6:
|
||
105 0008 20000E42 .word 1108213792
|
||
106 .cfi_endproc
|
||
107 .LFE67:
|
||
109 .section .text.HAL_PWR_DisableBkUpAccess,"ax",%progbits
|
||
110 .align 1
|
||
111 .global HAL_PWR_DisableBkUpAccess
|
||
112 .syntax unified
|
||
113 .thumb
|
||
114 .thumb_func
|
||
115 .fpu softvfp
|
||
117 HAL_PWR_DisableBkUpAccess:
|
||
118 .LFB68:
|
||
174:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
ARM GAS /tmp/cc2owkii.s page 6
|
||
|
||
|
||
175:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /**
|
||
176:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @brief Disables access to the backup domain (RTC registers, RTC
|
||
177:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * backup data registers).
|
||
178:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @note If the HSE divided by 128 is used as the RTC clock, the
|
||
179:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * Backup Domain Access should be kept enabled.
|
||
180:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @retval None
|
||
181:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */
|
||
182:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** void HAL_PWR_DisableBkUpAccess(void)
|
||
183:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** {
|
||
119 .loc 1 183 1 is_stmt 1 view -0
|
||
120 .cfi_startproc
|
||
121 @ args = 0, pretend = 0, frame = 0
|
||
122 @ frame_needed = 0, uses_anonymous_args = 0
|
||
123 @ link register save eliminated.
|
||
184:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Disable access to RTC and backup registers */
|
||
185:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** *(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE;
|
||
124 .loc 1 185 3 view .LVU13
|
||
125 .loc 1 185 32 is_stmt 0 view .LVU14
|
||
126 0000 014B ldr r3, .L9
|
||
127 0002 0022 movs r2, #0
|
||
128 0004 1A60 str r2, [r3]
|
||
186:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** }
|
||
129 .loc 1 186 1 view .LVU15
|
||
130 0006 7047 bx lr
|
||
131 .L10:
|
||
132 .align 2
|
||
133 .L9:
|
||
134 0008 20000E42 .word 1108213792
|
||
135 .cfi_endproc
|
||
136 .LFE68:
|
||
138 .section .text.HAL_PWR_ConfigPVD,"ax",%progbits
|
||
139 .align 1
|
||
140 .global HAL_PWR_ConfigPVD
|
||
141 .syntax unified
|
||
142 .thumb
|
||
143 .thumb_func
|
||
144 .fpu softvfp
|
||
146 HAL_PWR_ConfigPVD:
|
||
147 .LVL0:
|
||
148 .LFB69:
|
||
187:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
188:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /**
|
||
189:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @}
|
||
190:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */
|
||
191:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
192:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
|
||
193:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @brief Low Power modes configuration functions
|
||
194:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** *
|
||
195:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** @verbatim
|
||
196:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** ===============================================================================
|
||
197:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** ##### Peripheral Control functions #####
|
||
198:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** ===============================================================================
|
||
199:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
200:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** *** PVD configuration ***
|
||
201:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** =========================
|
||
202:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** [..]
|
||
203:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (+) The PVD is used to monitor the VDD power supply by comparing it to a
|
||
ARM GAS /tmp/cc2owkii.s page 7
|
||
|
||
|
||
204:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
|
||
205:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
206:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
|
||
207:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** than the PVD threshold. This event is internally connected to the EXTI
|
||
208:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** line16 and can generate an interrupt if enabled. This is done through
|
||
209:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** __HAL_PVD_EXTI_ENABLE_IT() macro.
|
||
210:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (+) The PVD is stopped in Standby mode.
|
||
211:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
212:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** *** WakeUp pin configuration ***
|
||
213:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** ================================
|
||
214:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** [..]
|
||
215:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (+) WakeUp pin is used to wake up the system from Standby mode. This pin is
|
||
216:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** forced in input pull-down configuration and is active on rising edges.
|
||
217:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (+) There is one WakeUp pin:
|
||
218:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** WakeUp Pin 1 on PA.00.
|
||
219:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
220:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** [..]
|
||
221:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
222:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** *** Low Power modes configuration ***
|
||
223:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** =====================================
|
||
224:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** [..]
|
||
225:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** The device features 3 low-power modes:
|
||
226:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (+) Sleep mode: CPU clock off, all peripherals including Cortex-M3 core peripherals like
|
||
227:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** NVIC, SysTick, etc. are kept running
|
||
228:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (+) Stop mode: All clocks are stopped
|
||
229:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (+) Standby mode: 1.8V domain powered off
|
||
230:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
231:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
232:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** *** Sleep mode ***
|
||
233:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** ==================
|
||
234:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** [..]
|
||
235:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (+) Entry:
|
||
236:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_S
|
||
237:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** functions with
|
||
238:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
|
||
239:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
|
||
240:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
241:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (+) Exit:
|
||
242:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (++) WFI entry mode, Any peripheral interrupt acknowledged by the nested vectored interrupt
|
||
243:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** controller (NVIC) can wake up the device from Sleep mode.
|
||
244:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (++) WFE entry mode, Any wakeup event can wake up the device from Sleep mode.
|
||
245:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (+++) Any peripheral interrupt w/o NVIC configuration & SEVONPEND bit set in the Cortex
|
||
246:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (+++) Any EXTI Line (Internal or External) configured in Event mode
|
||
247:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
248:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** *** Stop mode ***
|
||
249:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** =================
|
||
250:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** [..]
|
||
251:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** The Stop mode is based on the Cortex-M3 deepsleep mode combined with peripheral
|
||
252:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** clock gating. The voltage regulator can be configured either in normal or low-power mode.
|
||
253:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** In Stop mode, all clocks in the 1.8 V domain are stopped, the PLL, the HSI and the HSE RC
|
||
254:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** oscillators are disabled. SRAM and register contents are preserved.
|
||
255:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** In Stop mode, all I/O pins keep the same state as in Run mode.
|
||
256:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
257:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (+) Entry:
|
||
258:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_REGULATOR_VALUE, PWR_SLEEPE
|
||
259:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** function with:
|
||
260:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (++) PWR_REGULATOR_VALUE= PWR_MAINREGULATOR_ON: Main regulator ON.
|
||
ARM GAS /tmp/cc2owkii.s page 8
|
||
|
||
|
||
261:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (++) PWR_REGULATOR_VALUE= PWR_LOWPOWERREGULATOR_ON: Low Power regulator ON.
|
||
262:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (++) PWR_SLEEPENTRY_WFx= PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction
|
||
263:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (++) PWR_SLEEPENTRY_WFx= PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction
|
||
264:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (+) Exit:
|
||
265:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (++) WFI entry mode, Any EXTI Line (Internal or External) configured in Interrupt mode wi
|
||
266:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (++) WFE entry mode, Any EXTI Line (Internal or External) configured in Event mode.
|
||
267:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
268:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** *** Standby mode ***
|
||
269:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** ====================
|
||
270:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** [..]
|
||
271:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** The Standby mode allows to achieve the lowest power consumption. It is based on the
|
||
272:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** Cortex-M3 deepsleep mode, with the voltage regulator disabled. The 1.8 V domain is
|
||
273:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** consequently powered off. The PLL, the HSI oscillator and the HSE oscillator are also
|
||
274:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** switched off. SRAM and register contents are lost except for registers in the Backup domain
|
||
275:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** and Standby circuitry
|
||
276:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
277:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (+) Entry:
|
||
278:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
|
||
279:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (+) Exit:
|
||
280:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (++) WKUP pin rising edge, RTC alarm event rising edge, external Reset in
|
||
281:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** NRSTpin, IWDG Reset
|
||
282:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
283:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** *** Auto-wakeup (AWU) from low-power mode ***
|
||
284:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** =============================================
|
||
285:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** [..]
|
||
286:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
287:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (+) The MCU can be woken up from low-power mode by an RTC Alarm event,
|
||
288:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** without depending on an external interrupt (Auto-wakeup mode).
|
||
289:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
290:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (+) RTC auto-wakeup (AWU) from the Stop and Standby modes
|
||
291:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
292:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
|
||
293:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() functio
|
||
294:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
295:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** *** PWR Workarounds linked to Silicon Limitation ***
|
||
296:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** ====================================================
|
||
297:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** [..]
|
||
298:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** Below the list of all silicon limitations known on STM32F1xx prouct.
|
||
299:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
300:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (#)Workarounds Implemented inside PWR HAL Driver
|
||
301:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (##)Debugging Stop mode with WFE entry - overloaded the WFE by an internal function
|
||
302:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
303:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** @endverbatim
|
||
304:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @{
|
||
305:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */
|
||
306:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
307:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /**
|
||
308:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
|
||
309:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration
|
||
310:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * information for the PVD.
|
||
311:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @note Refer to the electrical characteristics of your device datasheet for
|
||
312:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * more details about the voltage threshold corresponding to each
|
||
313:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * detection level.
|
||
314:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @retval None
|
||
315:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */
|
||
316:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
|
||
317:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** {
|
||
ARM GAS /tmp/cc2owkii.s page 9
|
||
|
||
|
||
149 .loc 1 317 1 is_stmt 1 view -0
|
||
150 .cfi_startproc
|
||
151 @ args = 0, pretend = 0, frame = 0
|
||
152 @ frame_needed = 0, uses_anonymous_args = 0
|
||
153 @ link register save eliminated.
|
||
318:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Check the parameters */
|
||
319:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
|
||
154 .loc 1 319 3 view .LVU17
|
||
320:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
|
||
155 .loc 1 320 3 view .LVU18
|
||
321:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
322:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Set PLS[7:5] bits according to PVDLevel value */
|
||
323:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel);
|
||
156 .loc 1 323 3 view .LVU19
|
||
157 0000 1E4A ldr r2, .L16
|
||
158 0002 1368 ldr r3, [r2]
|
||
159 0004 23F0E003 bic r3, r3, #224
|
||
160 0008 0168 ldr r1, [r0]
|
||
161 000a 0B43 orrs r3, r3, r1
|
||
162 000c 1360 str r3, [r2]
|
||
324:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
325:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Clear any previous config. Keep it clear if no event or IT mode is selected */
|
||
326:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
|
||
163 .loc 1 326 3 view .LVU20
|
||
164 000e 1C4B ldr r3, .L16+4
|
||
165 0010 5A68 ldr r2, [r3, #4]
|
||
166 0012 22F48032 bic r2, r2, #65536
|
||
167 0016 5A60 str r2, [r3, #4]
|
||
327:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_DISABLE_IT();
|
||
168 .loc 1 327 3 view .LVU21
|
||
169 0018 1A68 ldr r2, [r3]
|
||
170 001a 22F48032 bic r2, r2, #65536
|
||
171 001e 1A60 str r2, [r3]
|
||
328:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
|
||
172 .loc 1 328 3 view .LVU22
|
||
173 0020 DA68 ldr r2, [r3, #12]
|
||
174 0022 22F48032 bic r2, r2, #65536
|
||
175 0026 DA60 str r2, [r3, #12]
|
||
329:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
|
||
176 .loc 1 329 3 view .LVU23
|
||
177 0028 9A68 ldr r2, [r3, #8]
|
||
178 002a 22F48032 bic r2, r2, #65536
|
||
179 002e 9A60 str r2, [r3, #8]
|
||
330:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
331:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Configure interrupt mode */
|
||
332:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
|
||
180 .loc 1 332 3 view .LVU24
|
||
181 .loc 1 332 17 is_stmt 0 view .LVU25
|
||
182 0030 4368 ldr r3, [r0, #4]
|
||
183 .loc 1 332 5 view .LVU26
|
||
184 0032 13F4803F tst r3, #65536
|
||
185 0036 04D0 beq .L12
|
||
333:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** {
|
||
334:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_ENABLE_IT();
|
||
186 .loc 1 334 5 is_stmt 1 view .LVU27
|
||
187 0038 114A ldr r2, .L16+4
|
||
188 003a 1368 ldr r3, [r2]
|
||
ARM GAS /tmp/cc2owkii.s page 10
|
||
|
||
|
||
189 003c 43F48033 orr r3, r3, #65536
|
||
190 0040 1360 str r3, [r2]
|
||
191 .L12:
|
||
335:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** }
|
||
336:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
337:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Configure event mode */
|
||
338:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
|
||
192 .loc 1 338 3 view .LVU28
|
||
193 .loc 1 338 17 is_stmt 0 view .LVU29
|
||
194 0042 4368 ldr r3, [r0, #4]
|
||
195 .loc 1 338 5 view .LVU30
|
||
196 0044 13F4003F tst r3, #131072
|
||
197 0048 04D0 beq .L13
|
||
339:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** {
|
||
340:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
|
||
198 .loc 1 340 5 is_stmt 1 view .LVU31
|
||
199 004a 0D4A ldr r2, .L16+4
|
||
200 004c 5368 ldr r3, [r2, #4]
|
||
201 004e 43F48033 orr r3, r3, #65536
|
||
202 0052 5360 str r3, [r2, #4]
|
||
203 .L13:
|
||
341:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** }
|
||
342:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
343:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Configure the edge */
|
||
344:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
|
||
204 .loc 1 344 3 view .LVU32
|
||
205 .loc 1 344 17 is_stmt 0 view .LVU33
|
||
206 0054 4368 ldr r3, [r0, #4]
|
||
207 .loc 1 344 5 view .LVU34
|
||
208 0056 13F0010F tst r3, #1
|
||
209 005a 04D0 beq .L14
|
||
345:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** {
|
||
346:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
|
||
210 .loc 1 346 5 is_stmt 1 view .LVU35
|
||
211 005c 084A ldr r2, .L16+4
|
||
212 005e 9368 ldr r3, [r2, #8]
|
||
213 0060 43F48033 orr r3, r3, #65536
|
||
214 0064 9360 str r3, [r2, #8]
|
||
215 .L14:
|
||
347:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** }
|
||
348:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
349:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
|
||
216 .loc 1 349 3 view .LVU36
|
||
217 .loc 1 349 17 is_stmt 0 view .LVU37
|
||
218 0066 4368 ldr r3, [r0, #4]
|
||
219 .loc 1 349 5 view .LVU38
|
||
220 0068 13F0020F tst r3, #2
|
||
221 006c 04D0 beq .L11
|
||
350:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** {
|
||
351:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
|
||
222 .loc 1 351 5 is_stmt 1 view .LVU39
|
||
223 006e 044A ldr r2, .L16+4
|
||
224 0070 D368 ldr r3, [r2, #12]
|
||
225 0072 43F48033 orr r3, r3, #65536
|
||
226 0076 D360 str r3, [r2, #12]
|
||
227 .L11:
|
||
352:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** }
|
||
ARM GAS /tmp/cc2owkii.s page 11
|
||
|
||
|
||
353:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** }
|
||
228 .loc 1 353 1 is_stmt 0 view .LVU40
|
||
229 0078 7047 bx lr
|
||
230 .L17:
|
||
231 007a 00BF .align 2
|
||
232 .L16:
|
||
233 007c 00700040 .word 1073770496
|
||
234 0080 00040140 .word 1073808384
|
||
235 .cfi_endproc
|
||
236 .LFE69:
|
||
238 .section .text.HAL_PWR_EnablePVD,"ax",%progbits
|
||
239 .align 1
|
||
240 .global HAL_PWR_EnablePVD
|
||
241 .syntax unified
|
||
242 .thumb
|
||
243 .thumb_func
|
||
244 .fpu softvfp
|
||
246 HAL_PWR_EnablePVD:
|
||
247 .LFB70:
|
||
354:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
355:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /**
|
||
356:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @brief Enables the Power Voltage Detector(PVD).
|
||
357:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @retval None
|
||
358:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */
|
||
359:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** void HAL_PWR_EnablePVD(void)
|
||
360:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** {
|
||
248 .loc 1 360 1 is_stmt 1 view -0
|
||
249 .cfi_startproc
|
||
250 @ args = 0, pretend = 0, frame = 0
|
||
251 @ frame_needed = 0, uses_anonymous_args = 0
|
||
252 @ link register save eliminated.
|
||
361:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Enable the power voltage detector */
|
||
362:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE;
|
||
253 .loc 1 362 3 view .LVU42
|
||
254 .loc 1 362 33 is_stmt 0 view .LVU43
|
||
255 0000 014B ldr r3, .L19
|
||
256 0002 0122 movs r2, #1
|
||
257 0004 1A60 str r2, [r3]
|
||
363:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** }
|
||
258 .loc 1 363 1 view .LVU44
|
||
259 0006 7047 bx lr
|
||
260 .L20:
|
||
261 .align 2
|
||
262 .L19:
|
||
263 0008 10000E42 .word 1108213776
|
||
264 .cfi_endproc
|
||
265 .LFE70:
|
||
267 .section .text.HAL_PWR_DisablePVD,"ax",%progbits
|
||
268 .align 1
|
||
269 .global HAL_PWR_DisablePVD
|
||
270 .syntax unified
|
||
271 .thumb
|
||
272 .thumb_func
|
||
273 .fpu softvfp
|
||
275 HAL_PWR_DisablePVD:
|
||
276 .LFB71:
|
||
364:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
ARM GAS /tmp/cc2owkii.s page 12
|
||
|
||
|
||
365:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /**
|
||
366:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @brief Disables the Power Voltage Detector(PVD).
|
||
367:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @retval None
|
||
368:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */
|
||
369:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** void HAL_PWR_DisablePVD(void)
|
||
370:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** {
|
||
277 .loc 1 370 1 is_stmt 1 view -0
|
||
278 .cfi_startproc
|
||
279 @ args = 0, pretend = 0, frame = 0
|
||
280 @ frame_needed = 0, uses_anonymous_args = 0
|
||
281 @ link register save eliminated.
|
||
371:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Disable the power voltage detector */
|
||
372:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE;
|
||
282 .loc 1 372 3 view .LVU46
|
||
283 .loc 1 372 33 is_stmt 0 view .LVU47
|
||
284 0000 014B ldr r3, .L22
|
||
285 0002 0022 movs r2, #0
|
||
286 0004 1A60 str r2, [r3]
|
||
373:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** }
|
||
287 .loc 1 373 1 view .LVU48
|
||
288 0006 7047 bx lr
|
||
289 .L23:
|
||
290 .align 2
|
||
291 .L22:
|
||
292 0008 10000E42 .word 1108213776
|
||
293 .cfi_endproc
|
||
294 .LFE71:
|
||
296 .section .text.HAL_PWR_EnableWakeUpPin,"ax",%progbits
|
||
297 .align 1
|
||
298 .global HAL_PWR_EnableWakeUpPin
|
||
299 .syntax unified
|
||
300 .thumb
|
||
301 .thumb_func
|
||
302 .fpu softvfp
|
||
304 HAL_PWR_EnableWakeUpPin:
|
||
305 .LVL1:
|
||
306 .LFB72:
|
||
374:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
375:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /**
|
||
376:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @brief Enables the WakeUp PINx functionality.
|
||
377:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable.
|
||
378:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * This parameter can be one of the following values:
|
||
379:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @arg PWR_WAKEUP_PIN1
|
||
380:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @retval None
|
||
381:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */
|
||
382:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
|
||
383:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** {
|
||
307 .loc 1 383 1 is_stmt 1 view -0
|
||
308 .cfi_startproc
|
||
309 @ args = 0, pretend = 0, frame = 0
|
||
310 @ frame_needed = 0, uses_anonymous_args = 0
|
||
311 @ link register save eliminated.
|
||
384:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Check the parameter */
|
||
385:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
|
||
312 .loc 1 385 3 view .LVU50
|
||
386:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Enable the EWUPx pin */
|
||
387:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** *(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)ENABLE;
|
||
ARM GAS /tmp/cc2owkii.s page 13
|
||
|
||
|
||
313 .loc 1 387 3 view .LVU51
|
||
314 .LBB6:
|
||
315 .LBI6:
|
||
316 .file 2 "Drivers/CMSIS/Include/cmsis_gcc.h"
|
||
1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//**
|
||
2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h
|
||
3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file
|
||
4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.0.4
|
||
5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 09. April 2018
|
||
6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/
|
||
7:Drivers/CMSIS/Include/cmsis_gcc.h **** /*
|
||
8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||
9:Drivers/CMSIS/Include/cmsis_gcc.h **** *
|
||
10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0
|
||
11:Drivers/CMSIS/Include/cmsis_gcc.h **** *
|
||
12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may
|
||
13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License.
|
||
14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at
|
||
15:Drivers/CMSIS/Include/cmsis_gcc.h **** *
|
||
16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0
|
||
17:Drivers/CMSIS/Include/cmsis_gcc.h **** *
|
||
18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software
|
||
19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||
20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||
21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and
|
||
22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License.
|
||
23:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
24:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H
|
||
26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H
|
||
27:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */
|
||
29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
|
||
30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion"
|
||
31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion"
|
||
32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter"
|
||
33:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */
|
||
35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin
|
||
36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0)
|
||
37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
38:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */
|
||
40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM
|
||
41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm
|
||
42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE
|
||
44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline
|
||
45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE
|
||
47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline
|
||
48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE
|
||
50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
|
||
51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN
|
||
53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__))
|
||
ARM GAS /tmp/cc2owkii.s page 14
|
||
|
||
|
||
54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED
|
||
56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used))
|
||
57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK
|
||
59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak))
|
||
60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED
|
||
62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1)))
|
||
63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT
|
||
65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
|
||
66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION
|
||
68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1)))
|
||
69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */
|
||
71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
|
||
72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
|
||
73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
|
||
74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; };
|
||
75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
|
||
76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||
77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE
|
||
79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
|
||
80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
|
||
81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
|
||
82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||
83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
|
||
84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))-
|
||
85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ
|
||
87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
|
||
88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
|
||
89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
|
||
90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||
91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
|
||
92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add
|
||
93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE
|
||
95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
|
||
96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
|
||
97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
|
||
98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||
99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
|
||
100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))-
|
||
101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ
|
||
103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
|
||
104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
|
||
105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
|
||
106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||
107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
|
||
108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add
|
||
109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED
|
||
ARM GAS /tmp/cc2owkii.s page 15
|
||
|
||
|
||
111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x)))
|
||
112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT
|
||
114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict
|
||
115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
116:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
117:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
118:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */
|
||
119:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface
|
||
120:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
|
||
121:Drivers/CMSIS/Include/cmsis_gcc.h **** @{
|
||
122:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
123:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
124:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts
|
||
126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
|
||
127:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes.
|
||
128:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void)
|
||
130:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
131:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory");
|
||
132:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
133:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
134:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
135:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
136:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts
|
||
137:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR.
|
||
138:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes.
|
||
139:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
140:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void)
|
||
141:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
142:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory");
|
||
143:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
144:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
145:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
146:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
147:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register
|
||
148:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the Control Register.
|
||
149:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Control Register value
|
||
150:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
151:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
|
||
152:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
153:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
154:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
155:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control" : "=r" (result) );
|
||
156:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
|
||
157:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
158:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
159:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
160:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
|
||
161:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
162:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register (non-secure)
|
||
163:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the non-secure Control Register when in secure mode.
|
||
164:Drivers/CMSIS/Include/cmsis_gcc.h **** \return non-secure Control Register value
|
||
165:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
166:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
|
||
167:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
ARM GAS /tmp/cc2owkii.s page 16
|
||
|
||
|
||
168:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
169:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
170:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
|
||
171:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
|
||
172:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
173:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
174:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
175:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
176:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
177:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register
|
||
178:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the Control Register.
|
||
179:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set
|
||
180:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
181:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
|
||
182:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
183:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
|
||
184:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
185:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
186:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
187:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
|
||
188:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
189:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register (non-secure)
|
||
190:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the non-secure Control Register when in secure state.
|
||
191:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set
|
||
192:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
193:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
|
||
194:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
195:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
|
||
196:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
197:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
198:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
199:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
200:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
201:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get IPSR Register
|
||
202:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the IPSR Register.
|
||
203:Drivers/CMSIS/Include/cmsis_gcc.h **** \return IPSR Register value
|
||
204:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
205:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void)
|
||
206:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
207:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
208:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
209:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
|
||
210:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
|
||
211:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
212:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
213:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
214:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
215:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get APSR Register
|
||
216:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the APSR Register.
|
||
217:Drivers/CMSIS/Include/cmsis_gcc.h **** \return APSR Register value
|
||
218:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
219:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void)
|
||
220:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
221:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
222:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
223:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, apsr" : "=r" (result) );
|
||
224:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
|
||
ARM GAS /tmp/cc2owkii.s page 17
|
||
|
||
|
||
225:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
226:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
227:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
228:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
229:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get xPSR Register
|
||
230:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the xPSR Register.
|
||
231:Drivers/CMSIS/Include/cmsis_gcc.h **** \return xPSR Register value
|
||
232:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void)
|
||
234:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
235:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
236:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
237:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
|
||
238:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
|
||
239:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
240:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
241:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
242:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
243:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer
|
||
244:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer (PSP).
|
||
245:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value
|
||
246:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
247:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void)
|
||
248:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
249:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
250:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
251:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp" : "=r" (result) );
|
||
252:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
|
||
253:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
254:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
255:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
256:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
|
||
257:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
258:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer (non-secure)
|
||
259:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s
|
||
260:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value
|
||
261:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
262:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
|
||
263:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
264:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
265:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
266:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
|
||
267:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
|
||
268:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
269:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
270:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
271:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
272:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
273:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer
|
||
274:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer (PSP).
|
||
275:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set
|
||
276:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
277:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
|
||
278:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
279:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
|
||
280:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
281:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
ARM GAS /tmp/cc2owkii.s page 18
|
||
|
||
|
||
282:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
283:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
|
||
284:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
285:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure)
|
||
286:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta
|
||
287:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set
|
||
288:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
289:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
|
||
290:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
291:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
|
||
292:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
293:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
294:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
295:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
296:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
297:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer
|
||
298:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer (MSP).
|
||
299:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value
|
||
300:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
301:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void)
|
||
302:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
303:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
304:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
305:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp" : "=r" (result) );
|
||
306:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
|
||
307:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
308:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
309:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
310:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
|
||
311:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
312:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer (non-secure)
|
||
313:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat
|
||
314:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value
|
||
315:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
316:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
|
||
317:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
318:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
319:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
320:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
|
||
321:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
|
||
322:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
323:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
324:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
325:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
326:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
327:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer
|
||
328:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer (MSP).
|
||
329:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set
|
||
330:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
331:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
|
||
332:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
333:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
|
||
334:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
335:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
336:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
337:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
|
||
338:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
ARM GAS /tmp/cc2owkii.s page 19
|
||
|
||
|
||
339:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer (non-secure)
|
||
340:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
|
||
341:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set
|
||
342:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
343:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
|
||
344:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
345:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
|
||
346:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
347:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
348:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
349:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
|
||
351:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
352:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Stack Pointer (non-secure)
|
||
353:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
|
||
354:Drivers/CMSIS/Include/cmsis_gcc.h **** \return SP Register value
|
||
355:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
|
||
357:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
358:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
359:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
360:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
|
||
361:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
|
||
362:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
363:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
364:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
365:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
366:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Stack Pointer (non-secure)
|
||
367:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
|
||
368:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfStack Stack Pointer value to set
|
||
369:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
370:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
|
||
371:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
372:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
|
||
373:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
374:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
375:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
376:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
377:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
378:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask
|
||
379:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the priority mask bit from the Priority Mask Register.
|
||
380:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value
|
||
381:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
382:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
|
||
383:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
384:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
385:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
386:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
|
||
387:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
|
||
388:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
389:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
390:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
391:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
|
||
392:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
393:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask (non-secure)
|
||
394:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg
|
||
395:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value
|
||
ARM GAS /tmp/cc2owkii.s page 20
|
||
|
||
|
||
396:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
397:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
|
||
398:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
399:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
400:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
401:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
|
||
402:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
|
||
403:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
404:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
405:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
406:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
407:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
408:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask
|
||
409:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Priority Mask Register.
|
||
410:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask
|
||
411:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
412:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
|
||
413:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
414:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
||
415:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
416:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
417:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
418:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
|
||
419:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
420:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask (non-secure)
|
||
421:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
|
||
422:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask
|
||
423:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
424:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
|
||
425:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
426:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
|
||
427:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
428:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
429:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
430:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
431:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||
432:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
|
||
433:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
|
||
434:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
435:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable FIQ
|
||
436:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
|
||
437:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes.
|
||
438:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
439:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void)
|
||
440:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
441:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie f" : : : "memory");
|
||
442:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
443:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
444:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
445:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
446:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable FIQ
|
||
447:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables FIQ interrupts by setting the F-bit in the CPSR.
|
||
448:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes.
|
||
449:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
450:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void)
|
||
451:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
452:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid f" : : : "memory");
|
||
ARM GAS /tmp/cc2owkii.s page 21
|
||
|
||
|
||
453:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
454:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
455:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
456:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
457:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority
|
||
458:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Base Priority register.
|
||
459:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value
|
||
460:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
461:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
|
||
462:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
463:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
464:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
465:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri" : "=r" (result) );
|
||
466:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
|
||
467:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
468:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
469:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
470:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
|
||
471:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
472:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority (non-secure)
|
||
473:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Base Priority register when in secure state.
|
||
474:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value
|
||
475:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
476:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
|
||
477:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
478:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
479:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
480:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
|
||
481:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
|
||
482:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
483:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
484:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
485:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
486:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
487:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority
|
||
488:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register.
|
||
489:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set
|
||
490:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
|
||
492:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
493:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
|
||
494:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
495:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
496:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
497:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
|
||
498:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
499:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority (non-secure)
|
||
500:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Base Priority register when in secure state.
|
||
501:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set
|
||
502:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
503:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
|
||
504:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
505:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
|
||
506:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
507:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
508:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
509:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
ARM GAS /tmp/cc2owkii.s page 22
|
||
|
||
|
||
510:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
511:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority with condition
|
||
512:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable
|
||
513:Drivers/CMSIS/Include/cmsis_gcc.h **** or the new value increases the BASEPRI priority level.
|
||
514:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set
|
||
515:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
516:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
|
||
517:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
518:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
|
||
519:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
520:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
521:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
522:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
523:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask
|
||
524:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Fault Mask register.
|
||
525:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value
|
||
526:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
527:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
|
||
528:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
529:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
530:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
531:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
|
||
532:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
|
||
533:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
534:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
535:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
536:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
|
||
537:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
538:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask (non-secure)
|
||
539:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Fault Mask register when in secure state.
|
||
540:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value
|
||
541:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
542:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
|
||
543:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
544:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
545:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
546:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
|
||
547:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
|
||
548:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
549:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
550:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
551:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
552:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
553:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask
|
||
554:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Fault Mask register.
|
||
555:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set
|
||
556:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
557:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
|
||
558:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
559:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
|
||
560:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
561:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
562:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
563:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
|
||
564:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
565:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask (non-secure)
|
||
566:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Fault Mask register when in secure state.
|
||
ARM GAS /tmp/cc2owkii.s page 23
|
||
|
||
|
||
567:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set
|
||
568:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
569:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
|
||
570:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
571:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
|
||
572:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
573:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
574:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
575:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||
576:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
|
||
577:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
|
||
578:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
579:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
580:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||
581:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
|
||
582:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
583:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
584:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit
|
||
585:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
|
||
586:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure
|
||
587:Drivers/CMSIS/Include/cmsis_gcc.h **** mode.
|
||
588:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
589:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
|
||
590:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value
|
||
591:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
592:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
|
||
593:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
594:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||
595:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||
596:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI
|
||
597:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U;
|
||
598:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
|
||
599:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
600:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim" : "=r" (result) );
|
||
601:Drivers/CMSIS/Include/cmsis_gcc.h **** return result;
|
||
602:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
603:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
604:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
605:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
|
||
606:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
607:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit (non-secure)
|
||
608:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
|
||
609:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always.
|
||
610:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
611:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in
|
||
612:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value
|
||
613:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
614:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
|
||
615:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
616:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
|
||
617:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI
|
||
618:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U;
|
||
619:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
|
||
620:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
621:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
|
||
622:Drivers/CMSIS/Include/cmsis_gcc.h **** return result;
|
||
623:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
ARM GAS /tmp/cc2owkii.s page 24
|
||
|
||
|
||
624:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
625:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
626:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
627:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
628:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
629:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer Limit
|
||
630:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
|
||
631:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure
|
||
632:Drivers/CMSIS/Include/cmsis_gcc.h **** mode.
|
||
633:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
634:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
|
||
635:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
|
||
636:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
637:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
|
||
638:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
639:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||
640:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||
641:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI
|
||
642:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit;
|
||
643:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
|
||
644:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
|
||
645:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
646:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
647:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
648:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
649:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
|
||
650:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
651:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure)
|
||
652:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
|
||
653:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored.
|
||
654:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
655:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s
|
||
656:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
|
||
657:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
658:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
|
||
659:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
660:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
|
||
661:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI
|
||
662:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit;
|
||
663:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
|
||
664:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
|
||
665:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
666:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
667:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
668:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
669:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
670:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
671:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit
|
||
672:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
|
||
673:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure
|
||
674:Drivers/CMSIS/Include/cmsis_gcc.h **** mode.
|
||
675:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
676:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
|
||
677:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value
|
||
678:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
679:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
|
||
680:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
ARM GAS /tmp/cc2owkii.s page 25
|
||
|
||
|
||
681:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||
682:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||
683:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI
|
||
684:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U;
|
||
685:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
|
||
686:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
687:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim" : "=r" (result) );
|
||
688:Drivers/CMSIS/Include/cmsis_gcc.h **** return result;
|
||
689:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
690:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
691:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
692:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
693:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
|
||
694:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
695:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit (non-secure)
|
||
696:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
|
||
697:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always.
|
||
698:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
699:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec
|
||
700:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value
|
||
701:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
702:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
|
||
703:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
704:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
|
||
705:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI
|
||
706:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U;
|
||
707:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
|
||
708:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
709:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
|
||
710:Drivers/CMSIS/Include/cmsis_gcc.h **** return result;
|
||
711:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
712:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
713:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
714:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
715:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
716:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
717:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit
|
||
718:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
|
||
719:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure
|
||
720:Drivers/CMSIS/Include/cmsis_gcc.h **** mode.
|
||
721:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
722:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
|
||
723:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
|
||
724:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
|
||
726:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||
728:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||
729:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI
|
||
730:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit;
|
||
731:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
|
||
732:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
|
||
733:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
734:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
735:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
736:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
737:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
|
||
ARM GAS /tmp/cc2owkii.s page 26
|
||
|
||
|
||
738:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
739:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit (non-secure)
|
||
740:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
|
||
741:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored.
|
||
742:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
743:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu
|
||
744:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer value to set
|
||
745:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
|
||
747:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
|
||
749:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI
|
||
750:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit;
|
||
751:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
|
||
752:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
|
||
753:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
754:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
755:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
756:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
757:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||
758:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
|
||
759:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
760:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
761:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
762:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get FPSCR
|
||
763:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Floating Point Status/Control register.
|
||
764:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Floating Point Status/Control register value
|
||
765:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
766:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
|
||
767:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
768:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||
769:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||
770:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr)
|
||
771:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed
|
||
772:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
|
||
773:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
|
||
774:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_arm_get_fpscr();
|
||
775:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
|
||
776:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
777:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
778:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
|
||
779:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
|
||
780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
781:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
|
||
782:Drivers/CMSIS/Include/cmsis_gcc.h **** return(0U);
|
||
783:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
784:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
785:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
786:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
787:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
788:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set FPSCR
|
||
789:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Floating Point Status/Control register.
|
||
790:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] fpscr Floating Point Status/Control value to set
|
||
791:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
|
||
793:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||
ARM GAS /tmp/cc2owkii.s page 27
|
||
|
||
|
||
795:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||
796:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr)
|
||
797:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed
|
||
798:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
|
||
799:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
|
||
800:Drivers/CMSIS/Include/cmsis_gcc.h **** __builtin_arm_set_fpscr(fpscr);
|
||
801:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
|
||
802:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
|
||
803:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
804:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
|
||
805:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)fpscr;
|
||
806:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
807:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
808:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
809:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
810:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */
|
||
811:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
812:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
813:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################## Core Instruction Access ######################### */
|
||
814:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
||
815:Drivers/CMSIS/Include/cmsis_gcc.h **** Access to dedicated instructions
|
||
816:Drivers/CMSIS/Include/cmsis_gcc.h **** @{
|
||
817:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
818:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
819:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2.
|
||
820:Drivers/CMSIS/Include/cmsis_gcc.h **** * For thumb1, use low register (r0-r7), specified by constraint "l"
|
||
821:Drivers/CMSIS/Include/cmsis_gcc.h **** * Otherwise, use general registers, specified by constraint "r" */
|
||
822:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__)
|
||
823:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
|
||
824:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r)
|
||
825:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r)
|
||
826:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
|
||
827:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
|
||
828:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r)
|
||
829:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r)
|
||
830:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
831:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
832:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
833:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief No Operation
|
||
834:Drivers/CMSIS/Include/cmsis_gcc.h **** \details No Operation does nothing. This instruction can be used for code alignment purposes.
|
||
835:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
836:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP() __ASM volatile ("nop")
|
||
837:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
838:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
839:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Interrupt
|
||
840:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o
|
||
841:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
842:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI() __ASM volatile ("wfi")
|
||
843:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
844:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
845:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
846:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Event
|
||
847:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Event is a hint instruction that permits the processor to enter
|
||
848:Drivers/CMSIS/Include/cmsis_gcc.h **** a low-power state until one of a number of events occurs.
|
||
849:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
850:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE() __ASM volatile ("wfe")
|
||
851:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
ARM GAS /tmp/cc2owkii.s page 28
|
||
|
||
|
||
852:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
853:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
854:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Send Event
|
||
855:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||
856:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
857:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV() __ASM volatile ("sev")
|
||
858:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
859:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
860:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
861:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Instruction Synchronization Barrier
|
||
862:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||
863:Drivers/CMSIS/Include/cmsis_gcc.h **** so that all instructions following the ISB are fetched from cache or memory,
|
||
864:Drivers/CMSIS/Include/cmsis_gcc.h **** after the instruction has been completed.
|
||
865:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
866:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void)
|
||
867:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
868:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("isb 0xF":::"memory");
|
||
869:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
870:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
871:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
872:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
873:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Synchronization Barrier
|
||
874:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Acts as a special kind of Data Memory Barrier.
|
||
875:Drivers/CMSIS/Include/cmsis_gcc.h **** It completes when all explicit memory accesses before this instruction complete.
|
||
876:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
877:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void)
|
||
878:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
879:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dsb 0xF":::"memory");
|
||
880:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
881:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
882:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
883:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
884:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Memory Barrier
|
||
885:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Ensures the apparent order of the explicit memory operations before
|
||
886:Drivers/CMSIS/Include/cmsis_gcc.h **** and after the instruction, without ensuring their completion.
|
||
887:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
888:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void)
|
||
889:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
890:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dmb 0xF":::"memory");
|
||
891:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
892:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
893:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
894:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
895:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (32 bit)
|
||
896:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x785
|
||
897:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse
|
||
898:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value
|
||
899:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
900:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
|
||
901:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
902:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
|
||
903:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_bswap32(value);
|
||
904:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
|
||
905:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
906:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
907:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
|
||
908:Drivers/CMSIS/Include/cmsis_gcc.h **** return result;
|
||
ARM GAS /tmp/cc2owkii.s page 29
|
||
|
||
|
||
909:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
910:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
911:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
912:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
913:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
914:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit)
|
||
915:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes
|
||
916:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse
|
||
917:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value
|
||
918:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
919:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
|
||
920:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
921:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
922:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
923:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
|
||
924:Drivers/CMSIS/Include/cmsis_gcc.h **** return result;
|
||
925:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
926:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
927:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
928:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
929:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit)
|
||
930:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For exam
|
||
931:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse
|
||
932:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value
|
||
933:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
934:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
|
||
935:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
936:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
|
||
937:Drivers/CMSIS/Include/cmsis_gcc.h **** return (int16_t)__builtin_bswap16(value);
|
||
938:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
|
||
939:Drivers/CMSIS/Include/cmsis_gcc.h **** int16_t result;
|
||
940:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
941:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
|
||
942:Drivers/CMSIS/Include/cmsis_gcc.h **** return result;
|
||
943:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
944:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
945:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
946:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
947:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
948:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Rotate Right in unsigned value (32 bit)
|
||
949:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Rotate Right (immediate) provides the value of the contents of a register rotated by a v
|
||
950:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op1 Value to rotate
|
||
951:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op2 Number of Bits to rotate
|
||
952:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Rotated value
|
||
953:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
954:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
|
||
955:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
956:Drivers/CMSIS/Include/cmsis_gcc.h **** op2 %= 32U;
|
||
957:Drivers/CMSIS/Include/cmsis_gcc.h **** if (op2 == 0U)
|
||
958:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
959:Drivers/CMSIS/Include/cmsis_gcc.h **** return op1;
|
||
960:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
961:Drivers/CMSIS/Include/cmsis_gcc.h **** return (op1 >> op2) | (op1 << (32U - op2));
|
||
962:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
963:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
964:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
965:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
ARM GAS /tmp/cc2owkii.s page 30
|
||
|
||
|
||
966:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Breakpoint
|
||
967:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Causes the processor to enter Debug state.
|
||
968:Drivers/CMSIS/Include/cmsis_gcc.h **** Debug tools can use this to investigate system state when the instruction at a particula
|
||
969:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value is ignored by the processor.
|
||
970:Drivers/CMSIS/Include/cmsis_gcc.h **** If required, a debugger can use it to store additional information about the break
|
||
971:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
972:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __BKPT(value) __ASM volatile ("bkpt "#value)
|
||
973:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
974:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
975:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
976:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse bit order of value
|
||
977:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the bit order of the given value.
|
||
978:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse
|
||
979:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value
|
||
980:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
981:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
|
||
317 .loc 2 981 31 view .LVU52
|
||
318 .LBB7:
|
||
982:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
983:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
319 .loc 2 983 3 view .LVU53
|
||
984:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
985:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||
986:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
|
||
987:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
|
||
988:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
||
320 .loc 2 988 4 view .LVU54
|
||
321 .syntax unified
|
||
322 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
|
||
323 0000 90FAA0F0 rbit r0, r0
|
||
324 @ 0 "" 2
|
||
325 .LVL2:
|
||
989:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
|
||
990:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
|
||
991:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
992:Drivers/CMSIS/Include/cmsis_gcc.h **** result = value; /* r will be reversed bits of v; first get LSB of v */
|
||
993:Drivers/CMSIS/Include/cmsis_gcc.h **** for (value >>= 1U; value != 0U; value >>= 1U)
|
||
994:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
995:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= 1U;
|
||
996:Drivers/CMSIS/Include/cmsis_gcc.h **** result |= value & 1U;
|
||
997:Drivers/CMSIS/Include/cmsis_gcc.h **** s--;
|
||
998:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
999:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= s; /* shift when v's highest bits are zero */
|
||
1000:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
1001:Drivers/CMSIS/Include/cmsis_gcc.h **** return result;
|
||
326 .loc 2 1001 3 view .LVU55
|
||
327 .loc 2 1001 3 is_stmt 0 view .LVU56
|
||
328 .thumb
|
||
329 .syntax unified
|
||
330 .LBE7:
|
||
331 .LBE6:
|
||
332 .loc 1 387 22 view .LVU57
|
||
333 0004 B0FA80F0 clz r0, r0
|
||
334 0008 024B ldr r3, .L25
|
||
335 000a 0344 add r3, r3, r0
|
||
336 000c 9B00 lsls r3, r3, #2
|
||
337 .loc 1 387 46 view .LVU58
|
||
ARM GAS /tmp/cc2owkii.s page 31
|
||
|
||
|
||
338 000e 0122 movs r2, #1
|
||
339 0010 1A60 str r2, [r3]
|
||
388:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** }
|
||
340 .loc 1 388 1 view .LVU59
|
||
341 0012 7047 bx lr
|
||
342 .L26:
|
||
343 .align 2
|
||
344 .L25:
|
||
345 0014 20808310 .word 277053472
|
||
346 .cfi_endproc
|
||
347 .LFE72:
|
||
349 .section .text.HAL_PWR_DisableWakeUpPin,"ax",%progbits
|
||
350 .align 1
|
||
351 .global HAL_PWR_DisableWakeUpPin
|
||
352 .syntax unified
|
||
353 .thumb
|
||
354 .thumb_func
|
||
355 .fpu softvfp
|
||
357 HAL_PWR_DisableWakeUpPin:
|
||
358 .LVL3:
|
||
359 .LFB73:
|
||
389:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
390:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /**
|
||
391:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @brief Disables the WakeUp PINx functionality.
|
||
392:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
|
||
393:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * This parameter can be one of the following values:
|
||
394:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @arg PWR_WAKEUP_PIN1
|
||
395:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @retval None
|
||
396:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */
|
||
397:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
|
||
398:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** {
|
||
360 .loc 1 398 1 is_stmt 1 view -0
|
||
361 .cfi_startproc
|
||
362 @ args = 0, pretend = 0, frame = 0
|
||
363 @ frame_needed = 0, uses_anonymous_args = 0
|
||
364 @ link register save eliminated.
|
||
399:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Check the parameter */
|
||
400:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
|
||
365 .loc 1 400 3 view .LVU61
|
||
401:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Disable the EWUPx pin */
|
||
402:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** *(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)DISABLE;
|
||
366 .loc 1 402 3 view .LVU62
|
||
367 .LBB8:
|
||
368 .LBI8:
|
||
981:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
369 .loc 2 981 31 view .LVU63
|
||
370 .LBB9:
|
||
983:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
371 .loc 2 983 3 view .LVU64
|
||
988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
|
||
372 .loc 2 988 4 view .LVU65
|
||
373 .syntax unified
|
||
374 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
|
||
375 0000 90FAA0F0 rbit r0, r0
|
||
376 @ 0 "" 2
|
||
377 .LVL4:
|
||
378 .loc 2 1001 3 view .LVU66
|
||
ARM GAS /tmp/cc2owkii.s page 32
|
||
|
||
|
||
379 .loc 2 1001 3 is_stmt 0 view .LVU67
|
||
380 .thumb
|
||
381 .syntax unified
|
||
382 .LBE9:
|
||
383 .LBE8:
|
||
384 .loc 1 402 22 view .LVU68
|
||
385 0004 B0FA80F0 clz r0, r0
|
||
386 0008 024B ldr r3, .L28
|
||
387 000a 0344 add r3, r3, r0
|
||
388 000c 9B00 lsls r3, r3, #2
|
||
389 .loc 1 402 46 view .LVU69
|
||
390 000e 0022 movs r2, #0
|
||
391 0010 1A60 str r2, [r3]
|
||
403:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** }
|
||
392 .loc 1 403 1 view .LVU70
|
||
393 0012 7047 bx lr
|
||
394 .L29:
|
||
395 .align 2
|
||
396 .L28:
|
||
397 0014 20808310 .word 277053472
|
||
398 .cfi_endproc
|
||
399 .LFE73:
|
||
401 .section .text.HAL_PWR_EnterSLEEPMode,"ax",%progbits
|
||
402 .align 1
|
||
403 .global HAL_PWR_EnterSLEEPMode
|
||
404 .syntax unified
|
||
405 .thumb
|
||
406 .thumb_func
|
||
407 .fpu softvfp
|
||
409 HAL_PWR_EnterSLEEPMode:
|
||
410 .LVL5:
|
||
411 .LFB74:
|
||
404:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
405:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /**
|
||
406:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @brief Enters Sleep mode.
|
||
407:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @note In Sleep mode, all I/O pins keep the same state as in Run mode.
|
||
408:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @param Regulator: Regulator state as no effect in SLEEP mode - allows to support portability f
|
||
409:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction.
|
||
410:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * When WFI entry is used, tick interrupt have to be disabled if not desired as
|
||
411:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * the interrupt wake up source.
|
||
412:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * This parameter can be one of the following values:
|
||
413:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
|
||
414:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
|
||
415:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @retval None
|
||
416:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */
|
||
417:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
|
||
418:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** {
|
||
412 .loc 1 418 1 is_stmt 1 view -0
|
||
413 .cfi_startproc
|
||
414 @ args = 0, pretend = 0, frame = 0
|
||
415 @ frame_needed = 0, uses_anonymous_args = 0
|
||
416 @ link register save eliminated.
|
||
419:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Check the parameters */
|
||
420:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* No check on Regulator because parameter not used in SLEEP mode */
|
||
421:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Prevent unused argument(s) compilation warning */
|
||
422:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** UNUSED(Regulator);
|
||
417 .loc 1 422 3 view .LVU72
|
||
ARM GAS /tmp/cc2owkii.s page 33
|
||
|
||
|
||
423:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
424:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
|
||
418 .loc 1 424 3 view .LVU73
|
||
425:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
426:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Clear SLEEPDEEP bit of Cortex System Control Register */
|
||
427:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
||
419 .loc 1 427 3 view .LVU74
|
||
420 0000 064A ldr r2, .L34
|
||
421 0002 1369 ldr r3, [r2, #16]
|
||
422 0004 23F00403 bic r3, r3, #4
|
||
423 0008 1361 str r3, [r2, #16]
|
||
428:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
429:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Select SLEEP mode entry -------------------------------------------------*/
|
||
430:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
|
||
424 .loc 1 430 3 view .LVU75
|
||
425 .loc 1 430 5 is_stmt 0 view .LVU76
|
||
426 000a 0129 cmp r1, #1
|
||
427 000c 03D0 beq .L33
|
||
431:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** {
|
||
432:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Request Wait For Interrupt */
|
||
433:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** __WFI();
|
||
434:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** }
|
||
435:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** else
|
||
436:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** {
|
||
437:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Request Wait For Event */
|
||
438:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** __SEV();
|
||
428 .loc 1 438 5 is_stmt 1 view .LVU77
|
||
429 .syntax unified
|
||
430 @ 438 "Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c" 1
|
||
431 000e 40BF sev
|
||
432 @ 0 "" 2
|
||
439:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** __WFE();
|
||
433 .loc 1 439 5 view .LVU78
|
||
434 @ 439 "Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c" 1
|
||
435 0010 20BF wfe
|
||
436 @ 0 "" 2
|
||
440:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** __WFE();
|
||
437 .loc 1 440 5 view .LVU79
|
||
438 @ 440 "Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c" 1
|
||
439 0012 20BF wfe
|
||
440 @ 0 "" 2
|
||
441:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** }
|
||
442:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** }
|
||
441 .loc 1 442 1 is_stmt 0 view .LVU80
|
||
442 .thumb
|
||
443 .syntax unified
|
||
444 0014 7047 bx lr
|
||
445 .L33:
|
||
433:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** }
|
||
446 .loc 1 433 5 is_stmt 1 view .LVU81
|
||
447 .syntax unified
|
||
448 @ 433 "Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c" 1
|
||
449 0016 30BF wfi
|
||
450 @ 0 "" 2
|
||
451 .thumb
|
||
452 .syntax unified
|
||
453 0018 7047 bx lr
|
||
ARM GAS /tmp/cc2owkii.s page 34
|
||
|
||
|
||
454 .L35:
|
||
455 001a 00BF .align 2
|
||
456 .L34:
|
||
457 001c 00ED00E0 .word -536810240
|
||
458 .cfi_endproc
|
||
459 .LFE74:
|
||
461 .section .text.HAL_PWR_EnterSTOPMode,"ax",%progbits
|
||
462 .align 1
|
||
463 .global HAL_PWR_EnterSTOPMode
|
||
464 .syntax unified
|
||
465 .thumb
|
||
466 .thumb_func
|
||
467 .fpu softvfp
|
||
469 HAL_PWR_EnterSTOPMode:
|
||
470 .LVL6:
|
||
471 .LFB75:
|
||
443:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
444:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /**
|
||
445:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @brief Enters Stop mode.
|
||
446:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @note In Stop mode, all I/O pins keep the same state as in Run mode.
|
||
447:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @note When exiting Stop mode by using an interrupt or a wakeup event,
|
||
448:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * HSI RC oscillator is selected as system clock.
|
||
449:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @note When the voltage regulator operates in low power mode, an additional
|
||
450:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * startup delay is incurred when waking up from Stop mode.
|
||
451:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * By keeping the internal regulator ON during Stop mode, the consumption
|
||
452:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * is higher although the startup time is reduced.
|
||
453:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @param Regulator: Specifies the regulator state in Stop mode.
|
||
454:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * This parameter can be one of the following values:
|
||
455:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
|
||
456:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
|
||
457:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction.
|
||
458:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * This parameter can be one of the following values:
|
||
459:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
|
||
460:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
|
||
461:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @retval None
|
||
462:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */
|
||
463:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
|
||
464:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** {
|
||
472 .loc 1 464 1 view -0
|
||
473 .cfi_startproc
|
||
474 @ args = 0, pretend = 0, frame = 0
|
||
475 @ frame_needed = 0, uses_anonymous_args = 0
|
||
476 .loc 1 464 1 is_stmt 0 view .LVU83
|
||
477 0000 08B5 push {r3, lr}
|
||
478 .LCFI0:
|
||
479 .cfi_def_cfa_offset 8
|
||
480 .cfi_offset 3, -8
|
||
481 .cfi_offset 14, -4
|
||
465:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Check the parameters */
|
||
466:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** assert_param(IS_PWR_REGULATOR(Regulator));
|
||
482 .loc 1 466 3 is_stmt 1 view .LVU84
|
||
467:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
|
||
483 .loc 1 467 3 view .LVU85
|
||
468:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
469:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Clear PDDS bit in PWR register to specify entering in STOP mode when CPU enter in Deepsleep */
|
||
470:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** CLEAR_BIT(PWR->CR, PWR_CR_PDDS);
|
||
484 .loc 1 470 3 view .LVU86
|
||
ARM GAS /tmp/cc2owkii.s page 35
|
||
|
||
|
||
485 0002 0F4A ldr r2, .L40
|
||
486 0004 1368 ldr r3, [r2]
|
||
487 0006 23F00203 bic r3, r3, #2
|
||
488 000a 1360 str r3, [r2]
|
||
471:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
472:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Select the voltage regulator mode by setting LPDS bit in PWR register according to Regulator p
|
||
473:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** MODIFY_REG(PWR->CR, PWR_CR_LPDS, Regulator);
|
||
489 .loc 1 473 3 view .LVU87
|
||
490 000c 1368 ldr r3, [r2]
|
||
491 000e 23F00103 bic r3, r3, #1
|
||
492 0012 1843 orrs r0, r0, r3
|
||
493 .LVL7:
|
||
494 .loc 1 473 3 is_stmt 0 view .LVU88
|
||
495 0014 1060 str r0, [r2]
|
||
474:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
475:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Set SLEEPDEEP bit of Cortex System Control Register */
|
||
476:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
||
496 .loc 1 476 3 is_stmt 1 view .LVU89
|
||
497 0016 0B4A ldr r2, .L40+4
|
||
498 0018 1369 ldr r3, [r2, #16]
|
||
499 001a 43F00403 orr r3, r3, #4
|
||
500 001e 1361 str r3, [r2, #16]
|
||
477:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
478:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Select Stop mode entry --------------------------------------------------*/
|
||
479:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** if(STOPEntry == PWR_STOPENTRY_WFI)
|
||
501 .loc 1 479 3 view .LVU90
|
||
502 .loc 1 479 5 is_stmt 0 view .LVU91
|
||
503 0020 0129 cmp r1, #1
|
||
504 0022 06D1 bne .L37
|
||
480:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** {
|
||
481:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Request Wait For Interrupt */
|
||
482:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** __WFI();
|
||
505 .loc 1 482 5 is_stmt 1 view .LVU92
|
||
506 .syntax unified
|
||
507 @ 482 "Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c" 1
|
||
508 0024 30BF wfi
|
||
509 @ 0 "" 2
|
||
510 .LVL8:
|
||
511 .thumb
|
||
512 .syntax unified
|
||
513 .L38:
|
||
483:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** }
|
||
484:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** else
|
||
485:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** {
|
||
486:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Request Wait For Event */
|
||
487:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** __SEV();
|
||
488:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** PWR_OverloadWfe(); /* WFE redefine locally */
|
||
489:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** PWR_OverloadWfe(); /* WFE redefine locally */
|
||
490:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** }
|
||
491:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Reset SLEEPDEEP bit of Cortex System Control Register */
|
||
492:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
||
514 .loc 1 492 3 view .LVU93
|
||
515 0026 074A ldr r2, .L40+4
|
||
516 0028 1369 ldr r3, [r2, #16]
|
||
517 002a 23F00403 bic r3, r3, #4
|
||
518 002e 1361 str r3, [r2, #16]
|
||
493:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** }
|
||
ARM GAS /tmp/cc2owkii.s page 36
|
||
|
||
|
||
519 .loc 1 493 1 is_stmt 0 view .LVU94
|
||
520 0030 08BD pop {r3, pc}
|
||
521 .LVL9:
|
||
522 .L37:
|
||
487:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** PWR_OverloadWfe(); /* WFE redefine locally */
|
||
523 .loc 1 487 5 is_stmt 1 view .LVU95
|
||
524 .syntax unified
|
||
525 @ 487 "Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c" 1
|
||
526 0032 40BF sev
|
||
527 @ 0 "" 2
|
||
488:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** PWR_OverloadWfe(); /* WFE redefine locally */
|
||
528 .loc 1 488 5 view .LVU96
|
||
529 .thumb
|
||
530 .syntax unified
|
||
531 0034 FFF7FEFF bl PWR_OverloadWfe
|
||
532 .LVL10:
|
||
489:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** }
|
||
533 .loc 1 489 5 view .LVU97
|
||
534 0038 FFF7FEFF bl PWR_OverloadWfe
|
||
535 .LVL11:
|
||
536 003c F3E7 b .L38
|
||
537 .L41:
|
||
538 003e 00BF .align 2
|
||
539 .L40:
|
||
540 0040 00700040 .word 1073770496
|
||
541 0044 00ED00E0 .word -536810240
|
||
542 .cfi_endproc
|
||
543 .LFE75:
|
||
545 .section .text.HAL_PWR_EnterSTANDBYMode,"ax",%progbits
|
||
546 .align 1
|
||
547 .global HAL_PWR_EnterSTANDBYMode
|
||
548 .syntax unified
|
||
549 .thumb
|
||
550 .thumb_func
|
||
551 .fpu softvfp
|
||
553 HAL_PWR_EnterSTANDBYMode:
|
||
554 .LFB76:
|
||
494:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
495:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /**
|
||
496:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @brief Enters Standby mode.
|
||
497:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @note In Standby mode, all I/O pins are high impedance except for:
|
||
498:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * - Reset pad (still available)
|
||
499:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * - TAMPER pin if configured for tamper or calibration out.
|
||
500:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * - WKUP pin (PA0) if enabled.
|
||
501:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @retval None
|
||
502:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */
|
||
503:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** void HAL_PWR_EnterSTANDBYMode(void)
|
||
504:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** {
|
||
555 .loc 1 504 1 view -0
|
||
556 .cfi_startproc
|
||
557 @ args = 0, pretend = 0, frame = 0
|
||
558 @ frame_needed = 0, uses_anonymous_args = 0
|
||
559 @ link register save eliminated.
|
||
505:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Select Standby mode */
|
||
506:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** SET_BIT(PWR->CR, PWR_CR_PDDS);
|
||
560 .loc 1 506 3 view .LVU99
|
||
561 0000 054A ldr r2, .L43
|
||
ARM GAS /tmp/cc2owkii.s page 37
|
||
|
||
|
||
562 0002 1368 ldr r3, [r2]
|
||
563 0004 43F00203 orr r3, r3, #2
|
||
564 0008 1360 str r3, [r2]
|
||
507:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
508:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Set SLEEPDEEP bit of Cortex System Control Register */
|
||
509:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
||
565 .loc 1 509 3 view .LVU100
|
||
566 000a 044A ldr r2, .L43+4
|
||
567 000c 1369 ldr r3, [r2, #16]
|
||
568 000e 43F00403 orr r3, r3, #4
|
||
569 0012 1361 str r3, [r2, #16]
|
||
510:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
511:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* This option is used to ensure that store operations are completed */
|
||
512:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** #if defined ( __CC_ARM)
|
||
513:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** __force_stores();
|
||
514:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** #endif
|
||
515:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Request Wait For Interrupt */
|
||
516:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** __WFI();
|
||
570 .loc 1 516 3 view .LVU101
|
||
571 .syntax unified
|
||
572 @ 516 "Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c" 1
|
||
573 0014 30BF wfi
|
||
574 @ 0 "" 2
|
||
517:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** }
|
||
575 .loc 1 517 1 is_stmt 0 view .LVU102
|
||
576 .thumb
|
||
577 .syntax unified
|
||
578 0016 7047 bx lr
|
||
579 .L44:
|
||
580 .align 2
|
||
581 .L43:
|
||
582 0018 00700040 .word 1073770496
|
||
583 001c 00ED00E0 .word -536810240
|
||
584 .cfi_endproc
|
||
585 .LFE76:
|
||
587 .section .text.HAL_PWR_EnableSleepOnExit,"ax",%progbits
|
||
588 .align 1
|
||
589 .global HAL_PWR_EnableSleepOnExit
|
||
590 .syntax unified
|
||
591 .thumb
|
||
592 .thumb_func
|
||
593 .fpu softvfp
|
||
595 HAL_PWR_EnableSleepOnExit:
|
||
596 .LFB77:
|
||
518:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
519:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
520:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /**
|
||
521:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
|
||
522:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
|
||
523:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * re-enters SLEEP mode when an interruption handling is over.
|
||
524:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * Setting this bit is useful when the processor is expected to run only on
|
||
525:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * interruptions handling.
|
||
526:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @retval None
|
||
527:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */
|
||
528:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** void HAL_PWR_EnableSleepOnExit(void)
|
||
529:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** {
|
||
597 .loc 1 529 1 is_stmt 1 view -0
|
||
ARM GAS /tmp/cc2owkii.s page 38
|
||
|
||
|
||
598 .cfi_startproc
|
||
599 @ args = 0, pretend = 0, frame = 0
|
||
600 @ frame_needed = 0, uses_anonymous_args = 0
|
||
601 @ link register save eliminated.
|
||
530:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Set SLEEPONEXIT bit of Cortex System Control Register */
|
||
531:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
|
||
602 .loc 1 531 3 view .LVU104
|
||
603 0000 024A ldr r2, .L46
|
||
604 0002 1369 ldr r3, [r2, #16]
|
||
605 0004 43F00203 orr r3, r3, #2
|
||
606 0008 1361 str r3, [r2, #16]
|
||
532:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** }
|
||
607 .loc 1 532 1 is_stmt 0 view .LVU105
|
||
608 000a 7047 bx lr
|
||
609 .L47:
|
||
610 .align 2
|
||
611 .L46:
|
||
612 000c 00ED00E0 .word -536810240
|
||
613 .cfi_endproc
|
||
614 .LFE77:
|
||
616 .section .text.HAL_PWR_DisableSleepOnExit,"ax",%progbits
|
||
617 .align 1
|
||
618 .global HAL_PWR_DisableSleepOnExit
|
||
619 .syntax unified
|
||
620 .thumb
|
||
621 .thumb_func
|
||
622 .fpu softvfp
|
||
624 HAL_PWR_DisableSleepOnExit:
|
||
625 .LFB78:
|
||
533:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
534:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
535:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /**
|
||
536:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
|
||
537:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
|
||
538:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * re-enters SLEEP mode when an interruption handling is over.
|
||
539:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @retval None
|
||
540:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */
|
||
541:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** void HAL_PWR_DisableSleepOnExit(void)
|
||
542:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** {
|
||
626 .loc 1 542 1 is_stmt 1 view -0
|
||
627 .cfi_startproc
|
||
628 @ args = 0, pretend = 0, frame = 0
|
||
629 @ frame_needed = 0, uses_anonymous_args = 0
|
||
630 @ link register save eliminated.
|
||
543:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Clear SLEEPONEXIT bit of Cortex System Control Register */
|
||
544:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
|
||
631 .loc 1 544 3 view .LVU107
|
||
632 0000 024A ldr r2, .L49
|
||
633 0002 1369 ldr r3, [r2, #16]
|
||
634 0004 23F00203 bic r3, r3, #2
|
||
635 0008 1361 str r3, [r2, #16]
|
||
545:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** }
|
||
636 .loc 1 545 1 is_stmt 0 view .LVU108
|
||
637 000a 7047 bx lr
|
||
638 .L50:
|
||
639 .align 2
|
||
640 .L49:
|
||
ARM GAS /tmp/cc2owkii.s page 39
|
||
|
||
|
||
641 000c 00ED00E0 .word -536810240
|
||
642 .cfi_endproc
|
||
643 .LFE78:
|
||
645 .section .text.HAL_PWR_EnableSEVOnPend,"ax",%progbits
|
||
646 .align 1
|
||
647 .global HAL_PWR_EnableSEVOnPend
|
||
648 .syntax unified
|
||
649 .thumb
|
||
650 .thumb_func
|
||
651 .fpu softvfp
|
||
653 HAL_PWR_EnableSEVOnPend:
|
||
654 .LFB79:
|
||
546:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
547:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
548:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /**
|
||
549:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @brief Enables CORTEX M3 SEVONPEND bit.
|
||
550:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
|
||
551:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * WFE to wake up when an interrupt moves from inactive to pended.
|
||
552:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @retval None
|
||
553:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */
|
||
554:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** void HAL_PWR_EnableSEVOnPend(void)
|
||
555:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** {
|
||
655 .loc 1 555 1 is_stmt 1 view -0
|
||
656 .cfi_startproc
|
||
657 @ args = 0, pretend = 0, frame = 0
|
||
658 @ frame_needed = 0, uses_anonymous_args = 0
|
||
659 @ link register save eliminated.
|
||
556:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Set SEVONPEND bit of Cortex System Control Register */
|
||
557:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
|
||
660 .loc 1 557 3 view .LVU110
|
||
661 0000 024A ldr r2, .L52
|
||
662 0002 1369 ldr r3, [r2, #16]
|
||
663 0004 43F01003 orr r3, r3, #16
|
||
664 0008 1361 str r3, [r2, #16]
|
||
558:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** }
|
||
665 .loc 1 558 1 is_stmt 0 view .LVU111
|
||
666 000a 7047 bx lr
|
||
667 .L53:
|
||
668 .align 2
|
||
669 .L52:
|
||
670 000c 00ED00E0 .word -536810240
|
||
671 .cfi_endproc
|
||
672 .LFE79:
|
||
674 .section .text.HAL_PWR_DisableSEVOnPend,"ax",%progbits
|
||
675 .align 1
|
||
676 .global HAL_PWR_DisableSEVOnPend
|
||
677 .syntax unified
|
||
678 .thumb
|
||
679 .thumb_func
|
||
680 .fpu softvfp
|
||
682 HAL_PWR_DisableSEVOnPend:
|
||
683 .LFB80:
|
||
559:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
560:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
561:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /**
|
||
562:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @brief Disables CORTEX M3 SEVONPEND bit.
|
||
563:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
|
||
ARM GAS /tmp/cc2owkii.s page 40
|
||
|
||
|
||
564:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * WFE to wake up when an interrupt moves from inactive to pended.
|
||
565:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @retval None
|
||
566:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */
|
||
567:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** void HAL_PWR_DisableSEVOnPend(void)
|
||
568:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** {
|
||
684 .loc 1 568 1 is_stmt 1 view -0
|
||
685 .cfi_startproc
|
||
686 @ args = 0, pretend = 0, frame = 0
|
||
687 @ frame_needed = 0, uses_anonymous_args = 0
|
||
688 @ link register save eliminated.
|
||
569:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Clear SEVONPEND bit of Cortex System Control Register */
|
||
570:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
|
||
689 .loc 1 570 3 view .LVU113
|
||
690 0000 024A ldr r2, .L55
|
||
691 0002 1369 ldr r3, [r2, #16]
|
||
692 0004 23F01003 bic r3, r3, #16
|
||
693 0008 1361 str r3, [r2, #16]
|
||
571:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** }
|
||
694 .loc 1 571 1 is_stmt 0 view .LVU114
|
||
695 000a 7047 bx lr
|
||
696 .L56:
|
||
697 .align 2
|
||
698 .L55:
|
||
699 000c 00ED00E0 .word -536810240
|
||
700 .cfi_endproc
|
||
701 .LFE80:
|
||
703 .section .text.HAL_PWR_PVDCallback,"ax",%progbits
|
||
704 .align 1
|
||
705 .weak HAL_PWR_PVDCallback
|
||
706 .syntax unified
|
||
707 .thumb
|
||
708 .thumb_func
|
||
709 .fpu softvfp
|
||
711 HAL_PWR_PVDCallback:
|
||
712 .LFB82:
|
||
572:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
573:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
574:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
575:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /**
|
||
576:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @brief This function handles the PWR PVD interrupt request.
|
||
577:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @note This API should be called under the PVD_IRQHandler().
|
||
578:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @retval None
|
||
579:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */
|
||
580:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** void HAL_PWR_PVD_IRQHandler(void)
|
||
581:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** {
|
||
582:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Check PWR exti flag */
|
||
583:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
|
||
584:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** {
|
||
585:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* PWR PVD interrupt user callback */
|
||
586:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** HAL_PWR_PVDCallback();
|
||
587:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
588:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Clear PWR Exti pending bit */
|
||
589:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
|
||
590:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** }
|
||
591:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** }
|
||
592:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
593:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /**
|
||
ARM GAS /tmp/cc2owkii.s page 41
|
||
|
||
|
||
594:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @brief PWR PVD interrupt callback
|
||
595:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @retval None
|
||
596:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */
|
||
597:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** __weak void HAL_PWR_PVDCallback(void)
|
||
598:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** {
|
||
713 .loc 1 598 1 is_stmt 1 view -0
|
||
714 .cfi_startproc
|
||
715 @ args = 0, pretend = 0, frame = 0
|
||
716 @ frame_needed = 0, uses_anonymous_args = 0
|
||
717 @ link register save eliminated.
|
||
599:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* NOTE : This function Should not be modified, when the callback is needed,
|
||
600:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** the HAL_PWR_PVDCallback could be implemented in the user file
|
||
601:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */
|
||
602:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** }
|
||
718 .loc 1 602 1 view .LVU116
|
||
719 0000 7047 bx lr
|
||
720 .cfi_endproc
|
||
721 .LFE82:
|
||
723 .section .text.HAL_PWR_PVD_IRQHandler,"ax",%progbits
|
||
724 .align 1
|
||
725 .global HAL_PWR_PVD_IRQHandler
|
||
726 .syntax unified
|
||
727 .thumb
|
||
728 .thumb_func
|
||
729 .fpu softvfp
|
||
731 HAL_PWR_PVD_IRQHandler:
|
||
732 .LFB81:
|
||
581:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Check PWR exti flag */
|
||
733 .loc 1 581 1 view -0
|
||
734 .cfi_startproc
|
||
735 @ args = 0, pretend = 0, frame = 0
|
||
736 @ frame_needed = 0, uses_anonymous_args = 0
|
||
737 0000 08B5 push {r3, lr}
|
||
738 .LCFI1:
|
||
739 .cfi_def_cfa_offset 8
|
||
740 .cfi_offset 3, -8
|
||
741 .cfi_offset 14, -4
|
||
583:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** {
|
||
742 .loc 1 583 3 view .LVU118
|
||
583:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** {
|
||
743 .loc 1 583 6 is_stmt 0 view .LVU119
|
||
744 0002 064B ldr r3, .L62
|
||
745 0004 5B69 ldr r3, [r3, #20]
|
||
583:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** {
|
||
746 .loc 1 583 5 view .LVU120
|
||
747 0006 13F4803F tst r3, #65536
|
||
748 000a 00D1 bne .L61
|
||
749 .L58:
|
||
591:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
750 .loc 1 591 1 view .LVU121
|
||
751 000c 08BD pop {r3, pc}
|
||
752 .L61:
|
||
586:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
753 .loc 1 586 5 is_stmt 1 view .LVU122
|
||
754 000e FFF7FEFF bl HAL_PWR_PVDCallback
|
||
755 .LVL12:
|
||
589:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** }
|
||
ARM GAS /tmp/cc2owkii.s page 42
|
||
|
||
|
||
756 .loc 1 589 5 view .LVU123
|
||
757 0012 024B ldr r3, .L62
|
||
758 0014 4FF48032 mov r2, #65536
|
||
759 0018 5A61 str r2, [r3, #20]
|
||
591:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****
|
||
760 .loc 1 591 1 is_stmt 0 view .LVU124
|
||
761 001a F7E7 b .L58
|
||
762 .L63:
|
||
763 .align 2
|
||
764 .L62:
|
||
765 001c 00040140 .word 1073808384
|
||
766 .cfi_endproc
|
||
767 .LFE81:
|
||
769 .text
|
||
770 .Letext0:
|
||
771 .file 3 "/usr/arm-none-eabi/include/machine/_default_types.h"
|
||
772 .file 4 "/usr/arm-none-eabi/include/sys/_stdint.h"
|
||
773 .file 5 "Drivers/CMSIS/Include/core_cm3.h"
|
||
774 .file 6 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h"
|
||
775 .file 7 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h"
|
||
776 .file 8 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h"
|
||
777 .file 9 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h"
|
||
778 .file 10 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h"
|
||
ARM GAS /tmp/cc2owkii.s page 43
|
||
|
||
|
||
DEFINED SYMBOLS
|
||
*ABS*:0000000000000000 stm32f1xx_hal_pwr.c
|
||
/tmp/cc2owkii.s:16 .text.PWR_OverloadWfe:0000000000000000 $t
|
||
/tmp/cc2owkii.s:23 .text.PWR_OverloadWfe:0000000000000000 PWR_OverloadWfe
|
||
/tmp/cc2owkii.s:48 .text.HAL_PWR_DeInit:0000000000000000 $t
|
||
/tmp/cc2owkii.s:55 .text.HAL_PWR_DeInit:0000000000000000 HAL_PWR_DeInit
|
||
/tmp/cc2owkii.s:76 .text.HAL_PWR_DeInit:0000000000000014 $d
|
||
/tmp/cc2owkii.s:81 .text.HAL_PWR_EnableBkUpAccess:0000000000000000 $t
|
||
/tmp/cc2owkii.s:88 .text.HAL_PWR_EnableBkUpAccess:0000000000000000 HAL_PWR_EnableBkUpAccess
|
||
/tmp/cc2owkii.s:105 .text.HAL_PWR_EnableBkUpAccess:0000000000000008 $d
|
||
/tmp/cc2owkii.s:110 .text.HAL_PWR_DisableBkUpAccess:0000000000000000 $t
|
||
/tmp/cc2owkii.s:117 .text.HAL_PWR_DisableBkUpAccess:0000000000000000 HAL_PWR_DisableBkUpAccess
|
||
/tmp/cc2owkii.s:134 .text.HAL_PWR_DisableBkUpAccess:0000000000000008 $d
|
||
/tmp/cc2owkii.s:139 .text.HAL_PWR_ConfigPVD:0000000000000000 $t
|
||
/tmp/cc2owkii.s:146 .text.HAL_PWR_ConfigPVD:0000000000000000 HAL_PWR_ConfigPVD
|
||
/tmp/cc2owkii.s:233 .text.HAL_PWR_ConfigPVD:000000000000007c $d
|
||
/tmp/cc2owkii.s:239 .text.HAL_PWR_EnablePVD:0000000000000000 $t
|
||
/tmp/cc2owkii.s:246 .text.HAL_PWR_EnablePVD:0000000000000000 HAL_PWR_EnablePVD
|
||
/tmp/cc2owkii.s:263 .text.HAL_PWR_EnablePVD:0000000000000008 $d
|
||
/tmp/cc2owkii.s:268 .text.HAL_PWR_DisablePVD:0000000000000000 $t
|
||
/tmp/cc2owkii.s:275 .text.HAL_PWR_DisablePVD:0000000000000000 HAL_PWR_DisablePVD
|
||
/tmp/cc2owkii.s:292 .text.HAL_PWR_DisablePVD:0000000000000008 $d
|
||
/tmp/cc2owkii.s:297 .text.HAL_PWR_EnableWakeUpPin:0000000000000000 $t
|
||
/tmp/cc2owkii.s:304 .text.HAL_PWR_EnableWakeUpPin:0000000000000000 HAL_PWR_EnableWakeUpPin
|
||
/tmp/cc2owkii.s:345 .text.HAL_PWR_EnableWakeUpPin:0000000000000014 $d
|
||
/tmp/cc2owkii.s:350 .text.HAL_PWR_DisableWakeUpPin:0000000000000000 $t
|
||
/tmp/cc2owkii.s:357 .text.HAL_PWR_DisableWakeUpPin:0000000000000000 HAL_PWR_DisableWakeUpPin
|
||
/tmp/cc2owkii.s:397 .text.HAL_PWR_DisableWakeUpPin:0000000000000014 $d
|
||
/tmp/cc2owkii.s:402 .text.HAL_PWR_EnterSLEEPMode:0000000000000000 $t
|
||
/tmp/cc2owkii.s:409 .text.HAL_PWR_EnterSLEEPMode:0000000000000000 HAL_PWR_EnterSLEEPMode
|
||
/tmp/cc2owkii.s:457 .text.HAL_PWR_EnterSLEEPMode:000000000000001c $d
|
||
/tmp/cc2owkii.s:462 .text.HAL_PWR_EnterSTOPMode:0000000000000000 $t
|
||
/tmp/cc2owkii.s:469 .text.HAL_PWR_EnterSTOPMode:0000000000000000 HAL_PWR_EnterSTOPMode
|
||
/tmp/cc2owkii.s:540 .text.HAL_PWR_EnterSTOPMode:0000000000000040 $d
|
||
/tmp/cc2owkii.s:546 .text.HAL_PWR_EnterSTANDBYMode:0000000000000000 $t
|
||
/tmp/cc2owkii.s:553 .text.HAL_PWR_EnterSTANDBYMode:0000000000000000 HAL_PWR_EnterSTANDBYMode
|
||
/tmp/cc2owkii.s:582 .text.HAL_PWR_EnterSTANDBYMode:0000000000000018 $d
|
||
/tmp/cc2owkii.s:588 .text.HAL_PWR_EnableSleepOnExit:0000000000000000 $t
|
||
/tmp/cc2owkii.s:595 .text.HAL_PWR_EnableSleepOnExit:0000000000000000 HAL_PWR_EnableSleepOnExit
|
||
/tmp/cc2owkii.s:612 .text.HAL_PWR_EnableSleepOnExit:000000000000000c $d
|
||
/tmp/cc2owkii.s:617 .text.HAL_PWR_DisableSleepOnExit:0000000000000000 $t
|
||
/tmp/cc2owkii.s:624 .text.HAL_PWR_DisableSleepOnExit:0000000000000000 HAL_PWR_DisableSleepOnExit
|
||
/tmp/cc2owkii.s:641 .text.HAL_PWR_DisableSleepOnExit:000000000000000c $d
|
||
/tmp/cc2owkii.s:646 .text.HAL_PWR_EnableSEVOnPend:0000000000000000 $t
|
||
/tmp/cc2owkii.s:653 .text.HAL_PWR_EnableSEVOnPend:0000000000000000 HAL_PWR_EnableSEVOnPend
|
||
/tmp/cc2owkii.s:670 .text.HAL_PWR_EnableSEVOnPend:000000000000000c $d
|
||
/tmp/cc2owkii.s:675 .text.HAL_PWR_DisableSEVOnPend:0000000000000000 $t
|
||
/tmp/cc2owkii.s:682 .text.HAL_PWR_DisableSEVOnPend:0000000000000000 HAL_PWR_DisableSEVOnPend
|
||
/tmp/cc2owkii.s:699 .text.HAL_PWR_DisableSEVOnPend:000000000000000c $d
|
||
/tmp/cc2owkii.s:704 .text.HAL_PWR_PVDCallback:0000000000000000 $t
|
||
/tmp/cc2owkii.s:711 .text.HAL_PWR_PVDCallback:0000000000000000 HAL_PWR_PVDCallback
|
||
/tmp/cc2owkii.s:724 .text.HAL_PWR_PVD_IRQHandler:0000000000000000 $t
|
||
/tmp/cc2owkii.s:731 .text.HAL_PWR_PVD_IRQHandler:0000000000000000 HAL_PWR_PVD_IRQHandler
|
||
/tmp/cc2owkii.s:765 .text.HAL_PWR_PVD_IRQHandler:000000000000001c $d
|
||
|
||
NO UNDEFINED SYMBOLS
|